Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 24, 2014 Inductive Noise 1 Penn ESE370 Fall2014 -- DeHon Today • Inductive Responses – Show math, but let’s not get bogged down in • • • • Calculating L Where do inductances show up Impact of inductance on digital circuits How address – Want to make sure we get to last two 2 Penn ESE370 Fall2014 -- DeHon Response • What happens here? 3 Penn ESE370 Fall2014 -- DeHon V2 dI L LC Response V V dt 2 dV2 I C dt d 2V2 CL V V 2 dt Penn ESE370 Fall2014 -- DeHon 4 LC Response V2 A Be wt d 2V2 CL V V 2 dt 5 Penn ESE370 Fall2014 -- DeHon LC Response V2 A Be dV2 2 wt w Be dt wt d 2V2 CL V V 2 dt Penn ESE370 Fall2014 -- DeHon 6 LC Response V2 A Be wt 2 d V2 w Be dt 2 wt d 2V2 CL V V 2 dt CLw Be 2 wt A Be wt V 7 Penn ESE370 Fall2014 -- DeHon LC Response CLw Be 2 V A Penn ESE370 Fall2014 -- DeHon wt A Be wt V CLw 1 0 2 1 w i CL 8 LC Response V A V2 A Be V2 V Be wt 1 w i CL 1 i t CL d 2V2 CL V V 2 dt Penn ESE370 Fall2014 -- DeHon 9 LC Response i e cos( ) isin( ) V2 V Be 1 i t CL 10 Penn ESE370 Fall2014 -- DeHon LC Response i V2 V Be 1 t CL 11 Penn ESE370 Fall2014 -- DeHon Response? 12 Penn ESE370 Fall2014 -- DeHon V2 RLC Response L dI dt IR V2 V dV2 I C dt d 2V2 dV2 V2 V CL RC dt dt 13 Penn ESE370 Fall2014 -- DeHon RLC Response V2 A Be wt dV2 2 wBe dt d V2 wt w Be dt 2 wt d 2V2 dV2 V2 V CL RC dt dt Penn ESE370 Fall2014 -- DeHon 14 RLC Response dV2 V2 A Be wt 2 d V2 wBe dt wt w Be dt 2 wt d 2V2 dV RC 2 V V CL 2 dt dt CLw Be 2 wt wt wt RC wBe A Be V 15 Penn ESE370 Fall2014 -- DeHon Solving for w CLw Be 2 RC wBe A Be CLw RC w 1 0 wt wt wt V 2 R 1 w w 0 L LC 2 Penn ESE370 Fall2014 -- DeHon 16 RLC R R 4 L LC L w 2 2 R 1 w w 0 L LC 2 17 Penn ESE370 Fall2014 -- DeHon RLC R R 4 L LC L w 2 2 V2 A Be wt 18 Penn ESE370 Fall2014 -- DeHon RLC • For R R 4 L LC L w 2 2 V2 A Be 4L R C • What happens? – Oscillation • Asumming R>0, what else happens? wt – Decay 19 Penn ESE370 Fall2014 -- DeHon RLC R R 4 L LC L w 2 2 V2 A Be • For 2 R 1 R w i 2L LC 2L wt V2 A Be Penn ESE370 Fall2014 -- DeHon 4L R C Rt 2L Decay e 2 1 R i t LC 2L Oscillation 20 RLC Response (R=100) 21 Penn ESE370 Fall2014 -- DeHon When Oscillate • For what R does this particular circuit oscillate? 4L R C 4L 200 C 22 Penn ESE370 Fall2014 -- DeHon RLC Response 23 Penn ESE370 Fall2014 -- DeHon Inductance of Wire 24 Penn ESE370 Fall2014 -- DeHon Inductance: Wire over Ground Plane 0 r h L l w • Inductance per cm with h=3mil, w=5mil? 25 Penn ESE370 Fall2014 -- DeHon Lwire CL C and L per unit length L Penn ESE370 Fall2014 -- DeHon C 26 Chip Inductance • Cwire = 0.16 pF for the 1mm) • Cwire = 0.16nF/m • Permeability 0≈ Si02=12.6×10-7H/m • Permitivity ox=3.5×10-11F/m L Penn ESE370 Fall2014 -- DeHon C 27 On Chip • Cwire = 0.16 pF for the 1mm) • Cwire = 0.16nF/m • Permeability 0≈ Si02=12.6×10-7H/m • Permitivity ox=3.5×10-11F/m 276pH (for 1 mm) L Penn ESE370 Fall2014 -- DeHon C 28 Comparisons • 5mil trace on PCB (preclass 2) • Protoboard wires (0.6mm diameter) – About 7nH/cm – http://www.consultrsr.com/resources/eis/induct5.htm • On chip wire – 0.28nH/mm = 2.8nH/cm 29 Penn ESE370 Fall2014 -- DeHon Inductors • • • • Bond pads Chip leads Long wire runs Cables Src: http://en.wikipedia.org/wiki/File:Wirebonding2.svg 30 Penn ESE370 Fall2014 -- DeHon Where Arise 31 Penn ESE370 Fall2014 -- DeHon Signal Path 32 Penn ESE370 Fall2014 -- DeHon Power Ground 33 Penn ESE370 Fall2014 -- DeHon Shared Power/Ground Example: 74x04 34 Penn ESE370 Fall2014 -- DeHon Estimate • Req, Ceq for gates in parallel – R0 = 25K W – C0 = 0.01 fF • say 10C0=0.1fF for typical load • • • • 250 gates switching at clock Req = 100WCeq=25fF R L Assume L=1nH w How long to settle? Oscillate? Penn ESE370 Fall2014 -- DeHon R 2 4 L LC 2 35 Power Ground 36 Penn ESE370 Fall2014 -- DeHon RLC Response 37 Penn ESE370 Fall2014 -- DeHon Today’s Chips • How many gates? 38 Penn ESE370 Fall2014 -- DeHon Multiple Power/Ground Pins • Use many power/ground pins • How many pins on a package? • Divide switching gates by pins – To get effective load on each pin 39 Penn ESE370 Fall2014 -- DeHon How Improve 40 Penn ESE370 Fall2014 -- DeHon How Improve? • Collect thoughts 41 Penn ESE370 Fall2014 -- DeHon Minimize the L • Make wires short • Use power and ground planes – Think of power plane as a very wide wire • Impact on C and L? 0 r h L l w 42 Penn ESE370 Fall2014 -- DeHon Flip Chip, Area IO www.microwavejournal.com http://www.izm.fraunhofer.de/en/abteilungen/high_density_interconnectwaferlevelpackaging/arbeitsgebiete/arbeitsgebiet1.html 43 Penn ESE370 Fall2014 -- DeHon Add Good C’s • Bypass Capacitors – inside the inductances – On board – On package – On chip 44 Penn ESE370 Fall2014 -- DeHon http://www.legitreviews.com/images/reviews/824/lga_compare.jpg Bypass Capacitor Example 45 Penn ESE370 Fall2014 -- DeHon Bypassed Supplies (@ transistor) 46 Penn ESE370 Fall2014 -- DeHon Bypassed Output 47 Penn ESE370 Fall2014 -- DeHon Minimize Current Draw • More Power/Ground Pins • Slower rise/fall times • Spread out switching 48 Penn ESE370 Fall2014 -- DeHon Idea • Long wires are inductive – Avoid them – Especially on power supplies • Bypass capacitors help Rt 2L V2 A Be e Penn ESE370 Fall2014 -- DeHon Decay R 2 R 4 L LC L w 2 V2 A Be 2 1 R i t LC 2L Oscillation 49 wt Admin • Tuesday: Project 2 due • Wednesday Lecture – Penn says “Wed. 11/26” is logically a Friday • Friday 11/28 is Thanksgiving Holiday 50 Penn ESE370 Fall2014 -- DeHon