Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 14: October 1, 2014 Layout and Area Midterm 1 Average: 79.7 (of 85) Std. Dev.: 4.4 Penn ESE370 Fall 2014 -- Townley & DeHon Problem 4 • Failure – my fault – Should be: min(max(3*(Va-Vb),0),1) • Failed to provide good diagnosis of restoration understanding – Noisy measurement • Result – Exam not provide very high precision assessment of students • Cannot distinguish A from B students Penn ESE370 Fall 2014 -- Townley & DeHon Exam Successes (not fail) • Does provide enough information to diagnose anyone ein big trouble and should drop – separate the DF from AB • Diagnose a few R C items – Need that down cold will use heavily • Did focus you on understanding these items, including restoration Penn ESE370 Fall 2014 -- Townley & DeHon Today • Layout – Transistors – Gates • Design rules • Standard cells 4 Penn ESE370 Fall 2014 -- Townley & DeHon Layout Penn ESE370 Fall 2014 -- Townley & DeHon Transistor Side view Perspective view 6 Penn ESE370 Fall 2014 -- Townley & DeHon Layout • Sizing & positioning of transistors • Designer controls W,L • tox fixed for process – Sometimes thick/thin oxide “flavors” Penn ESE370 Fall 2014 -- Townley & DeHon 7 NMOS Geometry L W Top view Perspective view 8 Penn ESE370 Fall 2014 -- Townley & DeHon NMOS Geometry L S G • Color scheme D – Red: gate – Green: source and drain areas (n type diffusion) W Top view 9 Penn ESE370 Fall 2014 -- Townley & DeHon NMOS vs PMOS • NMOS built on p substrate • PMOS built on n substrate – Needs an N-well Penn ESE370 Fall 2014 -- Townley & DeHon Rabaey text, Fig 2.1 10 PMOS Geometry L S G • Color scheme D W – Red: gate – Orange: source and drain areas (p type) – Green: n well • NMOS built on p wafer n well – Must add n material to build PMOS 11 Penn ESE370 Fall 2014 -- Townley & DeHon Body Contact • “Fourth terminal” • Needed to set voltage around device – PMOS: Vb = Vdd – NMOS: Vb = GND • At right: PMOS (orange) with body contact (dark green) 12 Penn ESE370 Fall 2014 -- Townley & DeHon Body Contact • Needed to set voltage around device – PMOS: Vb = Vdd – NMOS: Vb = GND • What happens if NMOS body contact is Vdd? 13 Penn ESE370 Fall 2014 -- Townley & DeHon Body Contact • Needed to set voltage around device – PMOS: Vb = Vdd – NMOS: Vb = GND • What happens if NMOS body contact is Vdd? – Polarity of field wrong – Won’t invert channel 14 Penn ESE370 Fall 2014 -- Townley & DeHon Body Contact • Needed to set voltage around device – PMOS: Vb = Vdd – NMOS: Vb = GND • Always to same supply as the transistor might be connected in CMOS 15 Penn ESE370 Fall 2014 -- Townley & DeHon Rotate All but PMOS Transistor 90 degrees Penn ESE370 Fall 2014 -- Townley & DeHon Interconnect • Connect transistors – Different layers of metal • “Contact” - metal to transistor • “Via” - metal to metal 17 Penn ESE370 Fall 2014 -- Townley & DeHon Interconnect • Connect transistors – Different layers of metal • “Contact” - metal to transistor • “Via” - metal to metal 18 Penn ESE370 Fall 2014 -- Townley & DeHon Interconnect Cross Section Penn ESE370 Fall 2014 -- Townley & DeHon ITRS 2007 19 Masks • Define areas want to see in layer – Think of “stencil” for material deposition • Use photoresist (PR) to form the “stencil” – Expose PR through mask – PR dissolves in exposed area – Material is deposited • Only “sticks” in area w/ dissolved PR 20 Penn ESE370 Fall 2014 -- Townley & DeHon Masking Process Mask Silicon wafer • Goal: draw a shape on the substrate – Simplest example: draw a rectangle 21 Penn ESE370 Fall 2014 -- Townley & DeHon Silicon wafer Masking Process Mask photoresist • First: deposit photoresist 22 Penn ESE370 Fall 2014 -- Townley & DeHon Masking Process • Expose through mask – UV light 23 Penn ESE370 Fall 2014 -- Townley & DeHon Masking Process • Remove mask and develop PR – Exposed area dissolves – This is “positive photoresist” 24 Penn ESE370 Fall 2014 -- Townley & DeHon Masking Process • Deposit metal through PR window – Then dissolve remaining PR • Why not just use mask? – Masks are expensive – Shine light through mask to etch PR – Can reuse mask 25 Penn ESE370 Fall 2014 -- Townley & DeHon Reverse Engineer Inverter Layout 26 Penn ESE370 Fall 2014 -- Townley & DeHon Layout Revisited • How to “decode” circuit from layout? 27 Penn ESE370 Fall 2014 -- Townley & DeHon Reverse Engineer Inverter Layout Power (Vdd) GND 28 Penn ESE370 Fall 2014 -- Townley & DeHon Reverse Engineer Inverter Layout Power (Vdd) • Where is PMOS transistor? • NMOS? GND 29 Penn ESE370 Fall 2014 -- Townley & DeHon Layout to Circuit • 1. Identify transistors 30 Penn ESE370 Fall Fall2010 2014----DeHon Townley & DeHon Inverter Layout • Where is Input? 31 Penn ESE370 Fall 2014 -- Townley & DeHon Inverter Layout • Where is Output? 32 Penn ESE370 Fall 2014 -- Townley & DeHon Layout to Circuit • 2. Add wires 33 Penn ESE370 Fall 2014 -- Townley & DeHon Layout to Circuit • 2. Add wires 34 Penn ESE370 Fall 2014 2010 -- Townley (DeHon) & DeHon Inverter Layout • What is structure at top and bottom? 35 Penn ESE370 Fall 2014 -- Townley & DeHon Layout to Circuit • 2. Add wires 36 Penn ESE370 Fall 2014 2010 -- Townley (DeHon) & DeHon Layout to Circuit • 2. Add wires 37 Penn ESE370 Fall 2014 2010 -- Townley (DeHon) & DeHon Design Rules • Why not adjacent transistors? – Plenty of empty space – If area is money, pack in as much as possible • Recall: processing imprecise – Margin of error for process variation 38 Penn ESE370 Fall 2014 -- Townley & DeHon Design Rules • Contract between process engineer & designer – Minimum width/spacing – Can be (often are) process specific • Lambda rules: scalable design rules – In terms of = 0.5 Lmin (Ldrawn) – Can migrate designs from similar process – Limited scope: 22nm process != 1m 39 Penn ESE370 Fall 2014 -- Townley & DeHon Design Rules: Some Examples 2 2 3 2 1.5 6 6 Legend Penn ESE370 Fall 2014 -- Townley & DeHon contact n doping metal 1 gate via p doping metal 2 Layout #2 (practice) 41 Penn ESE370 Fall 2014 -- Townley & DeHon Layout #2 (practice) • How many transistors? – PMOS? – NMOS? • How connected? – PMOS, NMOS? • Inputs connected? • Outputs? • What is it? 42 Penn ESE370 Fall 2014 -- Townley & DeHon Standard Cells • Lay out gates so that heights match – Rows of adjacent cells – Standardized sizes • Motivation: automated place and route – EDA tools convert HDL to layout 43 Penn ESE370 Fall 2014 -- Townley & DeHon Standard Cell Area All cells uniform height inv nand3 Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html Penn ESE370 Fall 2014 -- Townley & DeHon Standard Cell Layout Example http://www.laytools.com/images/StandardCells.jpg Penn ESE370 Fall 2014 -- Townley & DeHon ALU in Standard Cell http://www.erc.msstate.edu/mpl/distributions/scmos/images/alu_yon gchen.gif Penn ESE370 Fall 2014 -- Townley & DeHon Standard Cell Area All cells uniform height inv nand3 Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html Penn ESE370 Fall 2014 -- Townley & DeHon Big Idea • Layouts are physical realization of circuit – Geometry tradeoff • Can decrease spacing at the cost of yield • Design rules • Can go from circuit to layout or layout to circuit by inspection 48 Penn ESE370 Fall 2014 -- Townley & DeHon Admin • HW5 out – Due Tuesday – (Thursday next week is Fall Break) • Here on Friday Penn ESE370 Fall 2014 -- Townley & DeHon