ESE370: Circuit-Level

Modeling, Design, and Optimization

for Digital Systems

Day 13: October 3, 2012 Layout and Area Penn ESE370 Fall 2012 -- Townley & DeHon

Today

• Coping with Variation (from last time) • Layout – Transistors – Gates • Design rules • Standard cells Penn ESE370 Fall 2012 -- Townley & DeHon 2

Variation

• Margin for expected variation • Must assume V th – Speed  can be any value in range assume V th slowest value I on,min =I on (V th,max ) I d,sat  (V gs -V th ) 2 V TH Penn ESE370 Fall2012 -- DeHon 3

Variation

• See a range of parameters – L: L min – L max – V th : V th,min – V th,max • Validate design at extremes – Work for both V th,min and V th,max ?

– Design for worst-case scenario Penn ESE370 Fall2012 -- DeHon 4

Margining

• Also margin for – Temperature – Voltage – Aging: end-of-life Penn ESE370 Fall2012 -- DeHon 5

Process Corners

• Many effects independent • Many parameters • With N parameters, – Look only at extreme ends (low, high) – How many cases?

• Try to identify the {worst,best} set of parameters – Slow corner of design space, fast corner • Use corners to bracket behavior Penn ESE370 Fall2012 -- DeHon 6

Simple Corner Example

350mV What happens at various corners?

Vthp 150mV 150mV Vthn 350mV Penn ESE370 Fall2012 -- DeHon 7

Process Corners

• Many effects independent • Many parameters • Try to identify the {worst,best} set of parameters – E.g. Lump together things that make slow • Vthn, Vthp, temperature, Voltage • Try to reduce number of unique corners – Slow corner of design space • Use corners to bracket behavior 8 Penn ESE370 Fall2012 -- DeHon

Range of Behavior

• Still get range of performances • Any way to exploit the fact some are faster?

Delay Penn ESE370 Fall2012 -- DeHon 9

Speed Binning

Sell Premium Sell nominal Sell cheap Discard Delay Penn ESE370 Fall2012 -- DeHon 10

Penn ESE370 Fall 2012 -- Townley & DeHon

Layout

Transistor

Side view Penn ESE370 Fall 2012 -- Townley & DeHon Perspective view 12

Layout

• Sizing & positioning of transistors • Designer controls W,L • t ox fixed for process – Sometimes thick/thin oxide “flavors” Penn ESE370 Fall 2012 -- Townley & DeHon 13

W L

NMOS Geometry

Top view Penn ESE370 Fall 2012 -- Townley & DeHon Perspective view 14

W S L

NMOS Geometry

G D • Color scheme – Red : gate – Green : source and drain areas (n type diffusion) Top view Penn ESE370 Fall 2012 -- Townley & DeHon 15

t

ox • Transistors built by depositing materials – Constant rate of deposition (nm/min) – Time controls t ox • Oxides across entire chip deposited at same time – Same time interval – thickness is (roughly) constant – Process engineer sets value to: • Assure yield • What does t ox control?

– Field strength  V th , current – Achieve Performance, minimize leakage 16 Penn ESE370 Fall 2012 -- Townley & DeHon

NMOS vs PMOS

• Mostly talked about NMOS so far – PMOS: “opposite” in some sense – NMOS built on p substrate, PMOS built on n substrate – Name refers to bias/carriers when channel is inverted Penn ESE370 Fall 2012 -- Townley & DeHon Rabaey text, Fig 2.1

17

W S L

PMOS Geometry

G n well D • Color scheme – Red : gate – Orange : source and drain areas (p type) – Green : n well • NMOS built on p wafer – Must add n material to build PMOS 18 Penn ESE370 Fall 2012 -- Townley & DeHon

Body Contact

• “Fourth terminal” • Needed to set voltage around device – PMOS: V b – NMOS: V b = V dd = GND • At right: PMOS ( orange ) with body contact ( dark green ) Penn ESE370 Fall 2012 -- Townley & DeHon 19

Penn ESE370 Fall 2012 -- Townley & DeHon Rotate All but PMOS Transistor 90 degrees

Interconnect

• How to connect transistors – Different layers of metal Intermediate layers • “Contact” - metal to transistor • “Via” - metal to metal Penn ESE370 Fall 2012 -- Townley & DeHon 21

Interconnect

• How to connect transistors – Different layers of metal Intermediate layers • “Contact” - metal to transistor • “Via” - metal to metal Penn ESE370 Fall 2012 -- Townley & DeHon 22

Interconnect Cross Section

Penn ESE370 Fall 2012 -- Townley & DeHon ITRS 2007 23

Masks

• Define areas want to see in layer – Think of “stencil” for material deposition • Use photoresist (PR) to form the “stencil” – Expose PR through mask – PR dissolves in exposed area – Material is deposited • Only “sticks” in area w/ dissolved PR 24 Penn ESE370 Fall 2012 -- Townley & DeHon

Masking Process

Mask Silicon wafer • Goal: draw a shape on the substrate – Simplest example: draw a rectangle Penn ESE370 Fall 2012 -- Townley & DeHon 25

Silicon wafer

Masking Process

Mask photoresist • First: deposit photoresist Penn ESE370 Fall 2012 -- Townley & DeHon 26

Masking Process

• Expose through mask – UV light Penn ESE370 Fall 2012 -- Townley & DeHon 27

Masking Process

• Remove mask and develop PR – Exposed area dissolves – This is “positive photoresist” 28 Penn ESE370 Fall 2012 -- Townley & DeHon

Masking Process

• Deposit metal through PR window – Then dissolve remaining PR • Why not just use mask?

– Masks are expensive – Shine light through mask to etch PR – Can reuse mask 29 Penn ESE370 Fall 2012 -- Townley & DeHon

Logic Gates

• How to build complete inverter?

– Connect NMOS, PMOS using metal Penn ESE370 Fall 2012 -- Townley & DeHon 30

Inverter Layout Example

Penn ESE370 Fall 2012 -- Townley & DeHon 31

Inverter Layout Example

• Start with PMOS, NMOS transistors • Space for interconnect 32 Penn ESE370 Fall 2012 -- Townley & DeHon

Inverter Layout Example

Penn ESE370 Fall 2012 -- Townley & DeHon 33

Inverter Layout Example

• Add body contacts • Connect gates of transistors 34 Penn ESE370 Fall 2012 -- Townley & DeHon

Inverter Layout Example

Penn ESE370 Fall 2012 -- Townley & DeHon 35

Inverter Layout Example

• Add contacts to source, drain, gate, body • Connect using metal ( blue ) 36 Penn ESE370 Fall 2012 -- Townley & DeHon

Design Rules

• Why not adjacent transistors?

– Plenty of empty space – If area is money, pack in as much as possible • Recall: processing imprecise – Margin of error for process variation 37 Penn ESE370 Fall 2012 -- Townley & DeHon

Design Rules

• Contract between process engineer & designer – Minimum width/spacing – Can be (often are) process specific • Lambda rules: scalable design rules – In terms of  = 0.5 L min (L drawn ) – Can migrate designs from similar process – Limited scope: 45nm process != 1  m Penn ESE370 Fall 2012 -- Townley & DeHon 38

2  2  6  3  6 

Design Rules: Some Examples

  2  1.5



Legend

n doping gate p doping Penn ESE370 Fall 2012 -- Townley & DeHon contact metal 1 via metal 2

Layout Revisited

• How to “decode” circuit from layout?

40 Penn ESE370 Fall 2012 -- Townley & DeHon

Layout to Circuit

• 1. Identify transistors 41

Layout to Circuit

• 2. Add wires Penn ESE370 Fall 2012 -- Townley & DeHon 42

Layout to Circuit

• 2. Add wires 43

Layout to Circuit

• 2. Add wires 44

Layout to Circuit

• 2. Add wires 45

Layout #2 (practice)

Penn ESE370 Fall 2012 -- Townley & DeHon 46

Layout #2 (practice)

• How many transistors?

– PMOS?

– NMOS?

• How connected?

– PMOS, NMOS?

• Inputs connected?

• Outputs?

• What is it?

Penn ESE370 Fall 2012 -- Townley & DeHon 47

Standard Cells

• Lay out gates so that heights match – Rows of adjacent cells – Standardized sizes • Motivation: automated place and route – EDA tools convert HDL to layout 48 Penn ESE370 Fall 2012 -- Townley & DeHon

Standard Cell Area

inv nand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html

Penn ESE370 Fall 2012 -- Townley & DeHon

Admin

• HW4 due Thursday • Lecture on Friday • Review on Sunday at 6pm • Exam on Monday – No class at noon that day Penn ESE370 Fall 2012 -- Townley & DeHon

Big Idea

• Layouts are physical realization of circuit – Geometry tradeoff • Can decrease spacing at the cost of yield • Design rules • Can go from circuit to layout or layout to circuit by inspection 51 Penn ESE370 Fall 2012 -- Townley & DeHon