Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 36: December 6, 2010
Transmission Lines
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Penn ESE370 Fall2010 -- DeHon
Last week + today
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General wire formulation
Lossless Transmission Line
Reflections at ends of line
See in action in lab
Where arise?
Termination
Implications
Discuss Lossy
Penn ESE370 Fall2010 -- DeHon
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Transmission Lines
• This is what wires/cables look like
– Aren’t an ideal equipotential
– Signals do take time to propagate
– Shape and topology of wiring effects how
signals propagate
• …and the noise effects they see
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Transmission Lines
• Need to understand
– How to model  how to reason about
– What can cause noise
– How to engineer high performance
communication
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Transmission Lines
• Cable: coaxial
• PCB
– Strip line
– Microstrip line
• Twisted Pair (Cat5)
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Coaxial Cable
• Inner core conductor: radius r
• Insulator: out to radius R
• Outer core shield (ground)
   R 
L   ln  
2  r 
 1    R 
Z 0    ln  
2    r 
• RG-58 Z0= 50W – networking, lab
• (RG-59 Z0= 75W – video)
Penn ESE370 Fall2010 -- DeHon

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Printed Circuit Board
• Stripline
– Trace between planes
w
t
b
r


W


1
1  
b


Z 0    ln
t  W 
4    
 b
b 
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Penn ESE370 Fall2010 -- DeHon
Printed Circuit Board
• Microstrip line
– Trace over single supply plane
0
r
w
t
h
 
 1 


4h
ln 
Z 0   



2  0.475 r  0.67 0  0.536W  0.67t 
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Twisted Pair
• Category 5 ethernet cable
– 100W
– V=0.64c0
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Termination / Mismatch
• Wires do look like these transmission lines
• We are terminating them in some way
when we connect to gate
– Need to be deliberate about how terminate,
if we care about high performance
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Where Mismatch?
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Vias
Wire corners?
Connectors
Board-to-cable
Cable-to-cable
http://www.fpga4fun.com/Hands-on_Flashy.html
http://wiki.altium.com/display/ADOH/An+Overview+of+Electronic+Product+Development+in+Altium+Designer
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Visualization
• http://www.williamson-labs.com/xmission.htm
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Penn ESE370 Fall2010 -- DeHon
End of Line Reflection
R  Z 0 
Vr  Vi 

R  Z 0 

 2R 
Vt  Vi

R  Z 0 
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Termination Cases
• Parallel at Sink
– Pix
• Series at Source
– pix
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Pipeline Bits
• For properly terminated transmission line
– Do not need to wait for bits to arrive at sink
– Can stick new bits onto wire
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Limits to Bit Pipelining
• What limits?
– Risetime/distortion
– Clocking
• Skew
• Jitter
– For bus
• Wire length differences between lines
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Penn ESE370 Fall2010 -- DeHon
Eye Diagrams
• Watch bits over line on scope
– Look at distortion
– “open” eye clean place to sample
• Consistent timing of transitions
• Well defined high/low voltage levels
http://en.wikipedia.org/wiki/File:On-off_keying_eye_diagram.svg
http://focus.ti.com/analog/docs/gencontent.tsp?familyId=361&genContentId=41762&DCMP=ESD_Solutions&HQS=Other+OT+esd
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Bad “eye”
http://archive.chipcenter.com/knowledge_centers/asic/todays_feature/showArticle.jhtml?articleID=12800254
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Impedance Change
• What happens if there is an impedance
change in the wire?
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Z0=75, Z1=50
• At junction:
– Reflects
• Vr=(50-75)/(50+75)Vi
– Transmits
• Vt=(100/(50+75))Vi
R  Z 0 
Vi 
 Vr
R  Z0 
 2R 
Vi 
 Vt
R  Z 0 
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Impedance Change
Z0=75, Z1=50
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What happens at branch?
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Branch
• Transmission line sees two Z0 in parallel
– Looks like Z0/2
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Z0=50, Z1=25
• At junction:
– Reflects
• Vr=(25-50)/(25+50)Vi
– Transmits
• Vt=(50/(25+50))Vi
R  Z 0 
Vi 
 Vr
R  Z0 
 2R 
Vi 
 Vt
R  Z 0 
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End of Branch
• What happens at end?
• If ends in matched, parallel termination
– No further reflections
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Branch Simulation
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Branch with Open Circuit?
• What happens if branch open circuit?
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Branch with Open Circuit
• Reflects at end of open-circuit stub
• Reflection returns to branch
– …and encounters branch again
– Send transmission pulse to both
• Source and other branch
• Sink sees original pulse as multiple
smaller pulses spread out over time
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Open Branch Simulation
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Open Branch Simulation
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Bus
• Common to have many modules on a bus
– E.g. PCI slots
– DIM slots for memory
• High speed  bus lines are trans. lines
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Multi-drop Bus
• Ideal
– Open circuit, no load
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Multi-Drop Bus
• Capacitive load (stub) at drop?
– If tight/regular enough, change Z of line
L
Z0 
C
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Multi-Drop Bus
• Long wire stub?
– Looks like branch
• may produce reflections
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Lossy Transmission Line
• How do addition of R’s change?
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Penn ESE370 Fall2010 -- DeHon
Lossy Transmission Line
• R’s cause signal attenuation (loss)
– Voltage, energy
– Reduced signal swing at sink
– Limits length of transmission line before
need to restore signal
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Penn ESE370 Fall2010 -- DeHon
Transmission Line Noise
• Frequency limits
• Imperfect termination
• Mismatched
segments/junctions/vias/connectors
• Loss due to resistance in line
– Limits length
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Penn ESE370 Fall2010 -- DeHon
Admin
• Proj3b due Friday
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Idea
• Transmission lines
– high-speed
– high throughput
– long-distance signaling
• Termination
• Signal quality
1
c0
w

LC
 r r
L
Z0 
C
R  Z 0 
Vr  Vi 

 R  Z 0 

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