Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 18: October 20, 2010
Ratioed Logic
Pass Transistor Logic
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Penn ESE370 Fall2010 -- DeHon
Today
• Ratioed Gates
– Correctness
– Performance
– Power
– Implications
• Pass Transistor Logic
– Muxes
– Performance
– Composition
– Logic
Penn ESE370 Fall2010 -- DeHon
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Ratioed Logic Idea
• Maybe only need to
build one network
• Build NFET
pulldown
– Exploit high N
mobility
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Penn ESE370 Fall2010 -- DeHon
Size for R0/2 drive?
• …and Vol<0.1Vdd
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Compare Static CMOS
• Total Transistor Width
• Input capacitance load
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Power?
• Istatic ?
• Output high?
– Ileak
• Output low?
– Ipmos_on
– Vdd/(R0/2) -- for our sample case
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Penn ESE370 Fall2010 -- DeHon
Power
• Ptot ≈ a(½Cload+Csc)V2f
+PlowV2/Rpon
+(1-Plow)VI’s(W/L)e-Vt/(nkT/q)
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Penn ESE370 Fall2010 -- DeHon
How size for R0/2 drive?
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How size for R0/2 drive?
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Penn ESE370 Fall2010 -- DeHon
Which Implementation is
faster in ratioed logic?
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Illustrates
• Preferred gate changes
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How size for R0/2 drive?
• K-input nor
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When better than CMOS nor-k?
• Better = smaller, lower input capacitance
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Ratioed Logic
• Tradeoff noise margin for
– Reduced area? Capacitive load?
• Dissipates static power in one mode
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Admin
• Project: Due Friday
• Midterm: next Wednesday
– (one week from today)
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Pass Transistor Logic
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What does this do?
S
A
B
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Behavior
• What is the equivalent logic function?
S
A
B
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Size Comparison
• How does this compare to the static
CMOS alternative?
– transistor count?
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Delay
• Assume R0/2 drive
• 10C0 load
• What else need to know?
5
2
5
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Delay
• Assume R0/2 drive
• 10C0 load
• What else need to know?
5
– Cdiff
– Assume Cdiff≈Cgate
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5
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What’s different?
• What’s different about the output?
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Output ok?
• Is the output usable?
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CMOS DC Transfer Function
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After CMOS Inverter
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What does this do?
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Cascade Functional?
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Voltage Drop
• Voltage drop across any number of
series transistors is one Vth
• Think about two series transistors as
one transistor of twice the length
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Day 9
Pinch Off
• When voltage drops below VT, drops
out of inversion
– Occurs when: VGS-VDS< VT
• Conclusion:
– current cannot increase with VDS once
VDS> VGS-VT
– current must adjust so that VDS= VGS-VT
– If current dropped to zero, then would
invert and conduct again…
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Performance?
• Assume R0/2 drive
• 10C0 load
• Cdiff=Cgate
5
2
5
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Penn ESE370 Fall2010 -- DeHon
What does this do?
A
B
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Performance
• R0/2 drive
• 10C0 load
5
2
5
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Performance
• R0/2 drive
• 10C0 load
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Not Isolating
• Does not isolate downstream capacitive load
• Stage delay now dependent on downstream
stages
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Penn ESE370 Fall2010 -- DeHon
Ideas
• There are other logic disciplines
• We have the tools to analyze
• Ratioed Logic
– Tradeoff noise margin for
• Reduced area? Capacitive load?
– Dissipates static power in one mode
• Pass Transistor Logic
– Possibly smaller
– Not rail-to-rail
– Cascading without buffering  slow
Penn ESE370 Fall2010 -- DeHon
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