Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 32: November 24, 2010
Uncorrelated Noise Sources
Ionizing, Thermal, Shot
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Penn ESE370 Fall2010 -- DeHon
Today
• Ionizing Particles
• Thermal Noise
• Shot Noise
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Ionizing Particles
• Alpha Particles (He nucleus=He2+)
• Impact with mega-electron-volts of
energy (3—10MeV)
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Ionizing Particles
• Alpha Particles (He nucleus=He2+)
• Can penetrate microns into Si
• Creating 2×106 electron-hole pairs
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Ionizing Particles
• Alpha Particles (He nucleus=He2+)
• Can be generated by decay in
packaging materials
– Lead common one including some fraction
of radioactive isotopes 210Pb
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Src: http://en.wikipedia.org/wiki/File:Wirebonding2.svg
Comparisons
• How many electrons in:
– Capacitor: 1fF charges to 1V
– e = 1.6×10-19 Coulombs
• Recall C0 = 0.01fF,
– typical load around 10-20C0
• How large a capacitor to withstand loss
of 2×106 electrons?
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Disrupt
• Alpha particle will disrupt DRAM Cell
• Can disrupt undriven nodes
– Latch
– Dynamic node
– Memory bit
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Ionizing Particles
• There are other particles with different
energies
– Neutrons from cosmic rays
• 10x energy of alpha particles
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Particle Flux
• Differs with location
– Altitude
• Denver vs. Philadelphia
• Ground vs. aircraft at 30,000 feet
• Space (outside atmosphere)
– Near poles
• Changes upset rate seen by chips
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LLNSD October 2005
[Quinn and Graham/FCCM2005]
Soft Error Failure Rate Projections
1 FIT = 1 Failure per 109 hours of operation
LLNSD October 2005
[Heather Quinn 2005]
Scaling
• Charge holding memory decreases
– More susceptible
• Cross-sectional area of bit decreases
– Each bit less likely to be hit
– Hit may be large enough to take out multiple
bits at a time
• More bits on the chip
– More targets!  more likely something gets hit
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Driven Node
• What happens if the alpha particle
impacts a driven node?
• Will recover
– Creates a glitch
– May slow down node
– Only a problem if latched into register
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Driven Failure
• Driven input to latch -- value failure?
– When is it a problem?
• Occurs at end of cycle
– Right at last transition time for node
• Occurs earlier
– Not expecting value to have settled
• Occurs later
– May not propagate to latch
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Logic Failure Rate
Pfail
T 
upset
 
T 
Pstrike
 cycle 
• Probability will see
increases with
increasing frequency
• Tupset ~ picoseconds?
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Frequency Dependence
Gill (Intel), IEEE International Reliability Physics Symposium 2009
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SEU/bit Norm to 130nm
Scaling and Error Rates
Increasing Error Rates
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2X bit/latch count increase per
generation
logic
cache
arrays
1
180
130
90
65
45
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Technology (nm)
Penn ESE370 Fall2010 -- DeHon
Source: Carter/Intel
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Thermal Noise
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Thermal Background
• Except at absolute 0 (Temperature)
– Particles are moving around randomly
• Thermal bath means free energy
around
• Electron can be borrow the thermal
energy to hop over barrier
– Out of an energy well, bond cite
– …Out of a capacitor
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Day 8
Doping with P
• End up with extra electrons
– Donor electrons
• Not tightly bound to atom
– Low energy to displace
– Easy for these electrons
to move
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Day 8
Doped Band Gaps
• Addition of donor electrons makes more
metallic
– Easier to conduct
Semiconductor
0.045ev
1.1ev
Ec
ED
Ev
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Day 8
Electron Conduction
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Thermal Background
• Except at absolute 0 (Temperature)
– Particles are moving around randomly
• Thermal bath means free energy
around
• Electron can be borrow the thermal
energy to hop over barrier
• Are doing it all the time to give us our
semiconductors
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Rising above
the Thermal Noise
• Must apply more energy than
background noise to
– Hold electron in place
– Move an electron from place to place
• Charge/discharge a node with some reliability
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Minimum Energy
• Single bit gate output
– Set from previous value to 0 or 1
– Reduce state space by factor of 2
– Entropy: S= k×ln(before/after)=k×ln2
– Energy=T S=kT×ln(2)
• Setting a bit costs at least kT×ln(2)
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Probability of Noise Error
• This minimum energy around kT is just
to have 50% probability of setting bit
correctly
• Probability exponential in energy
– Not exactly this…but basic dependence
Perror  e
 E 
 
kT 
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Implication
• To keep error rate sufficiently low
– Need energy of operation (of storage) to be
some multiple of kT
Perror  e
 E 
 
kT 
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Where are we today?
• How does kT compare to switching
10C0 at 1V?
– k=1.4×10-23 J/K
– T=300K (Room Temperature)
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Where are we today?
• How does kT compare to switching
10C0 at 1V?
– k=1.4×10-23 J/K
– T=300K (Room Temperature)
• kT=4.2×10-21 J
• Eswitch=CV2 = 0.1fJ=10-16J
• Eswitch~=2×104 kT
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Scaling
• Eswitch~=2×104 kT
• 45nm to 4.5nm  impact on Eswitch?
– reduce capacitance by 10x
– reduce voltage by 2x
– Eswitch~=500 kT
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Relate kT to electrons
• If we arrange the capacitor to hold a
single electron
– What storage/switching just equals 1 kT?
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Chip Reliability
• Chip has many transistors
• …And many switching events
• Each of which may fail
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Chip Upset Rates
Kish, Physics Letters A 205 144—149 (2002)
Penn ESE370 Fall2010 -- DeHon
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Shot Noise
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Shot Noise
• Actual electron transport is probabilistic
• Current is a statement about average
rate of electron flow
• For large numbers of electrons
– Law of large numbers convergence to
mean
 s ~= Sqrt(N)
– Large N  sqrt(N)/N small
• Small percentage variation
Penn ESE370 Fall2010 -- DeHon
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Shot Noise
• For small number of electrons (N)
 s ~= Sqrt(N)
– sqrt(N)/N not so small
– Higher variation
– Noise in switching time
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Electron Counts
• How many electrons (N)
– in 0.1fF, 1V switching event?
– in 0.01fF, 0.5V switching event?
 s?
• How many s out to only get 50% of
electrons moving?
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Will we see?
• Large chips, fast clock rates  many
events….samples far out on curve
From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg
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Penn ESE534 Spring2010 -- DeHon
Gaussian Distrubution
Number Sigma
1 in How many
1
2
3
4
5
6
3.2
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370
16K
1.7 M
510M
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Admin
• Class Monday
• Lab on Wednesday or Friday (TBD)
– Class other day
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Idea
• Many sources cause upsets
– Ionizing particles, thermal, shot noise
• Tend to depend on charge
– Of node, of switching even
• Scaling decreases charge
– Lower voltage, lower capacitance
• Also increases susceptible nodes
– Also increases frequency susceptibility
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