Transcript talk

Understand the influence of frequency in
power and energy saving for certain
CMOS technology (180nm and 32nm)
 Understand the influence of frequency in
power and energy saving between
180nm and 32nm CMOS technology

 Ptotal
 Ptran
 Pstat
= Ptran + Psc + Pstat
2
fck CVDD /2
=α
= Isub VDD

Short-Circuit Energy
Increases with rise and fall times of input.
Decreases for larger output load
capacitance.
Decreases and eventually becomes zero
when VDD is scaled down but the
threshold voltages are not scaled down.
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Number of inputs: 35
Number of outputs: 49
Number of DFFs: 179
Number of gates: 2958 (counted in Powersim, one
DFF counted as one gate)
Number of vectors: 10
Use Matlab to convert Benchmark netliest
into rugster netlist
 Generate some random vectors as input
signals
 Set conditions and do the simulation

180nm Technology at 1.8V
Clock
rate
short circuit
power
leakage
power
transition
power
Total power
Energy per
cycle
40MHz
0
4.368uW
46.177uW
50.545uW
1263.6uWns
20Mhz
0
4.418uW
23.089uW
27.507uW
1375.4uWns
10Mhz
0
4.443uW
11.544uW
15.987uW
1598.7uWns
5Mhz
0
4.456uW
5.772uW
10.228uW
2045.6uWns
2.5Mhz
0
4.462uW
2.886uW
7.348uW
2939.2uwns
32nm technology at 0.9V
Clock
rate
short circuit
power
leakage
power
transition
power
Total power
Energy /
cycle
40MHz
0
4.368uW
11.544uW
15.912uW
397.8uWns
20Mhz
0
4.418uW
5.772uW
10.190uW
509.5uWns
10Mhz
0
4.443uW
2.886uW
7.329uW
732.9uWns
5Mhz
0
4.456uW
1.443uW
5.899uW
1179.8uWns
2.5Mhz
0
4.462uW
0.722uW
5.184uW
2073.6uWns
Ptran(180nm)/Ptran(32nm)=4
Clock slowdown has impact in power
saving not energy saving, and it is not
significant when frequency becomes
very slow because the leakage power
becomes more important.
 For 32nm CMOS technology, leakage
power become extremely significant in
proportion of the total power.
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Need to find other simulation tools to do the gate
level power simulation
Try to use Hspice to do the transistor level power
simulation based on some small circuit
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question?