Transcript Design of benchmark circuit (s5378) for reduced scan mode activity

Low Power Implementation of
Scan Flip-Flops
Chris Erickson
Graduate Student
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
Objectives
Scan flip-flop overview
Ways to incorporate low power design
Benchmark circuit
Results
Scan Flip-Flop
Primary
inputs
Primary
outputs
Combinational
logic
Scan-out
SO
Scan enable
SE
Scan-in
SI
Scan
flipflops
D
D
SI
0
1
SO
mux
D’
SE
DFF
D’
How does is work?
Primary
inputs
Combinational
logic
Primary
outputs
Scan-out
100
FF=0
FF=0
FF=1
Scan-in
010
Low Power Scan Flip-Flop
SO
SI
D
DFF
0
D’
SI
1
mux
D
mux
SO
DFF
SE
SE
Scan FF cell
Low power scan FF cell
D’
Validation of lpsff
Q grounds upon entering scan-mode
QS provides output to scan chain
Benchmark Circuit
S5378
– 35 Inputs
– 49 Outputs
Standard
– 179 D-type flip-flops
– 1775 Inverters
– 239 Or gates
– 765 Nor gates
Flattened/optimized
– Scan FF
967 complex gates
– Low-Power Scan FF
1152 complex gates
Test Patterns
Primary Input
Patterns
55 h
Primary
inputs
Combinational
logic
Primary
outputs
AA h
Scan-out
All 1s
All 0s
FF
Random but
constant 1
FF
Random but
constant 2
FF
All Random
Scan-in
Always Random
Gate Transitions
900
800
700
600
500
sff
lpsff
400
300
200
100
0
55h
AAh All 1 All 0 Rand Rand All
1
2 Rand
Gate Events
800
700
600
500
sff
lpsff
400
300
200
100
0
55h
AAh All 1
All 0 Rand Rand All
1
2
Rand
Average Power Consumption (uW)
40
35
30
25
sff
lpsff
20
15
10
5
0
55h
AAh All 1
All 0 Rand Rand
1
2
All
Rand
Power Reduction
55 h
sff  lpsff
35.1%
AA h
22.8%
All 1
22.9%
All 0
33.0%
Random 1 (const)
23.9%
Random 2 (const)
18.8%
All Random *
0% *
* Only encountered if entering into scan mode and the system
didn’t know to latch the input signals.
Conclusion
Low Power Scan Chain can result in up to
35% power reduction.
Minimal 19% area overhead from standard
scan chain flip-flop
Average power reduction of 20-30% if
input signals are held static
References
TSMC 0.25um process parameters
Mentor Graphics Leonardo for design
synthesis
Auburn’s PowerSim3 used for power
measurements – Created by : Jins
Alexander