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CMOS邏輯元件
CD4006
-- ================================================================================
-- CD4006 18-Stage Static Shift Register
--- Copyright (C),2013 Dr. C.H. Wei, STUST
--- This program is provided free of charge for educational purposes
--- Redistribution and use in binary form without modification, is permitted provided that the above copyright notice, this list of conditions
-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
-- ================================================================================
CD4006.VHD
library
use
ieee;
ieee.std_logic_1164.all;
entity CD4006 is
port (
CLK_n
D1
D2
D3
D4
D1_13
D2_11
D3_10
D2_12
D4_8
D4_9
end entity CD4006;
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in
in
in
in
in
out
out
out
out
out
out
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic);
CD4006.VHD
architecture behaviour of CD4006 is
-- Shift registers
signal
s1
: std_logic_vector (1 to 4)
signal
s2
: std_logic_vector (1 to 5)
signal
s3
: std_logic_vector (1 to 4)
signal
s4
: std_logic_vector (1 to 5)
begin
-- Shift the contents on falling edge of clock
process
(CLK_n,D1,D2,D3,D4)
begin
if falling_edge (CLK_n) then
s1 <= D1 & s1(1 to 3);
s2 <= D2 & s2(1 to 3);
s3 <= D3 & s3(1 to 4);
s4 <= D4 & s4(1 to 4);
end if;
end process;
-- Extract outputs from shift registers
D1_13 <= '1' when s1(4) = '1' else '0' ;
D2_11 <= '1' when s2(4) = '1' else '0' ;
D2_12 <= '1' when s2(5) = '1' else '0' ;
D3_10 <= '1' when s3(4) = '1' else '0' ;
D4_8 <= '1' when s4(4) = '1' else '0' ;
D4_9 <= '1' when s4(5) = '1' else '0' ;
end architecture;
:= "UUUU";
:= "UUUUU";
:= "UUUU";
:= "UUUUU";