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Exact Wiring Fault Minimization via Comprehensive
Layout Synthesis for CMOS Logic Cells
Tetsuya Iizuka, Makoto Ikeda and Kunihiro Asada
IEICE Technical Report, vol. 103, no. 476, pp. 157 - 161, Nov. 2003.
Presenter: Shui He Chen
Outline
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What is the Critical Area
Fault Model
Critical Areas Calculation
Layout Style
Comprehensive Layout Synthesis
Experimental Results
Transmission Electron Microscopy (TEM)
Critical Areas Calculation (1/2)
P  P0 min D( x) A( x)dx
X 02
D( x)  3
x
L( x )  ( x  l )  ( x  d )
 x 2  xd  xl  ld
 x 2  x(l  d )  ld
max
D(x): Defect Density
(1)
A(x): Defect Area
X0: Peak Defect Size
(2)
x: Spot Defect Size
(3)
l: Length
d: Space
x: Defect Size
d  l  l 2  2ld  d 2
 (l  d )  (l  d ) 2  4ld

x
2
2
 l 2  2ld  d 2  (l  d ) 2
d l l d
x 
d
2
OR
d l l d
x
 l
2
Critical Areas Calculation (2/2)
1
PL  P0 X 0 min L( x)dx
3
2
S L  d
2d w
max
(5)
P: Probability
( x  l )( x  d )
max ( 2d  w  l )( d  w)
dx  2 d  w
dx
3
3
x
x
2d  w l  d 1
1
 ln

( 
)
d
2 d 2d  w
2d  w d  w
S R  ln

d
2d  w
(7)
S: Sensitivity
(8)
R: Rectangles
(6)
The Critical Area Between Parallel Wire
Segments
L
w
x
d
X-d
x/2
The Critical Area
End Effect
x/2
X-d
The Critical Area at the Corner
x
X-d
The Critical Area
End Effect
The Redundant Critical Area
R(x)=(x-d)2
(4)
X-d
The Critical Area at the Opposing
X-d
x
End Effect
Layout Styles (1/8)
1. Static Dual CMOS Logic Circuits.
VDD
VDD
P-Type
Vin
Vout
Vin
Vout
Vin
Vout
N-Type
GND
GND
Layout Styles (2/8)
2. Transistors are Drawn up in two Horizontal Rows, the Upper Row
for P-MOSFETs and the Bottom Row for N-MOSFETs.
P-Type
N-Type
Layout Styles (3/8)
3. Two Transistors that Have the Same GATE Terminals are
Vertically Aligned.
P-Type
N-Type
Layout Styles (4/8)
4. All Transistors are Uniform-Size.
P-Type
N-Type
Layout Styles (5/8)
5. The Intra-Cell Routing uses Only First Metal Layers.
Layout Styles (6/8)
6. VDD are Connected From the top of P-Diffusion to the top
Boundary by the Vertical First Metal.
VDD
P-Type
N-Type
Layout Styles (7/8)
7. GND are Connected form the Bottom of N-Diffusion to the
Bottom Boundary by the Vertical First Metal.
P-Type
N-Type
GND
Layout Styles (8/8)
8. It is Assumed Enough to Place Single Contact from Metal to
Diffusion or Polysilicon.
VDD
P-Type
N-Type
GND
Grid Models Used in our Cell Layout
Synthesis System
Before Routing
After Routing
NWELL
P-Diffusion
POLY
N-Diffusion
The Flow Diagram of our Comprehensive Router
A Grid Model Problem
yes
Finish All Columns ?
All Possible
Routing Patterns
no
yes
Finish All Previous
Patterns ?
Check each Pattern is
Valid or not in the Next
Column
no
Determine the Pattern to
be Routed in Current
Column
Generate All Possible
Ports Patterns to the
Next Column
Find Split Nets and
Generate All Possible
Connections
Determine the Nets to
be Extended to the Next
Column
The Results of Comprehensive Cell
Layout Synthesis
Circuit
Name
#tr.
ao222
14
9
32
8
aoi21
6
4
4
4
999
0.36
aoi211
8
5
4
4
8839
eno
10
6
2
1
gen2
12
8
24
mux2
12
9
nand4
8
xnor2
10
Cell Synth. Selection Minimum
#col. #Place #Route #Layout CPU(sec.) CPU(sec.) Sensitivity Ave.Sensitivity Reduction
Wire-length-min. Ration(%)
948852 14685.04 323.70
18.04
20.55
12.19
0.17
5.37
6.56
18.10
1.70
1.60
6.08
7.13
14.77
19648
13.70
4.45
11.35
13.33
14.93
2
34120
20.55
10.38
17.78
20.90
14.91
144
4
392
6449.82
0.19
31.72
33.79
6.10
5
4
4
38366
3.01
6.92
5.37
6.38
15.78
7
144
29
27414
2164.30
6.97
11.18
15.27
26.81
Changes in Layout Sensitivity to Spot Defects
(a) Wire Length Minimum
(b) Sensitivity to Spot Defects Minimum
Sensitivity : 33.34
Sensitivity : 31.72
Wire Length : 60.0(nm)
Wire Length : 63.0(nm)