Transcript Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution

Speculative Lock Elision:
Enabling Highly Concurrent
Multithreaded Execution
Ravi Rajwar and Jams R. Goodman
Presented by Yang Liu
CPS221 Spring 2008
Outline
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Why want to elide locks?
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How to elide locks? – SLE
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Why does SLE work correctly?
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How to implement SLE?
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How is performance improved?
Why want to elide locks?
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Locks force serialization
Not all locks are required
How to elide locks?
- Atomicity conditions
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Within a speculatively executing critical section
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Read data is not modified by another thread before
section ends
Written data is not accessed by another thread
before section ends
How to elide locks?
- Eliding silent pairs
How to elide locks? - Steps
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Predict lock release store (silent pairs)
Predict atomicity and elide lock acquire
Execute critical section speculatively and
buffer results
If no atomicity, trigger misspeculation,
recover and explicitly acquire lock
If lock release store is seen, elide lock
release, commit state and exit section
How to elide locks? - Example
How to elide locks? - Example
Lock Acquire
How to elide locks? - Example
Lock Acquire
How to elide locks? - Example
Lock Acquire
Lock Release
Why does SLE work correctly?
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Two predictions
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Predict lock release store
Resolved by monitoring memory location of the stores
Predict memory operation atomicity
Resolved by checking atomicity conditions using
cache coherence mechanisms
How to implement SLE? – Four Aspects
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Initiating speculation
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Filter, index, confidence metric
Buffering speculative state
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Speculative register state
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ROB
Register checkpointing
Speculative memory state
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Augmented write-buffers
How to implement SLE? – Four Aspects
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Misspeculation conditions and detection
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Atomicity violations
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Violations due to limited resources
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ROB
Register checkpointing with access bit
Finite cache/write-buffer/ROB size
Uncached accesses or events
Committing speculative memory state
How to implement SLE?
How is performance improved?
- Evaluation methodology
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Three multiprocessor systems
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CMP/SMP/DSM
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A simple microbenchmark and six applications
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Single register checkpoint
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32-entry lock predictor indexed by PC
How is performance improved?
- Microbenchmark result
How is performance improved?
- Application result
How is performance improved?
- Application result
Some thoughts
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Idea is good
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Remove unnecessary serialization
Make programmers’ work easier
No results for using ROB
Why padding the benchmarks to reduce false
sharing?
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Shouldn’t this be done by SLE?