Transcript Presentation

Network for Computational Nanotechnology
Purdue, Norfolk State, Northwestern, UC Berkeley-MIT-Molecular Foundry, Univ. of Illinois, UTEP
Atomistic Modeling of Ultra-Scaled
III-V, Si/Ge, Graphene, and
Single Impurity Devices
Gerhard Klimeck, Mathieu Luisier, Rajib Rahman, S-H Park,
Hoon Ryu, Sunhee Lee,
Neerav Kharche, Purdue
Lloyd Hollenberg, Melbourne
Sven Rogge, G. Lansbergen, Delft
Thanks to
Gerhard Klimeck
Industrial Device Trends and Challenges
SiGe S/D
Strained Si
Robert Chau (Intel), 2004
Observations:
• 3D spatial variations on nm scale
• Potential variations on nm scale
• New channel materials (Ge, III-V)
Gerhard Klimeck
Questions / Challenges
• Strain ?
• Quantization?
• Crystal orientation?
• Atoms are countable; does
granularity matter? Disorder?
• New material or new device?
Assertions of importance
• High bias / non-equilibrium
• Quantum mechanics
• Atomistic representation
» Band coupling, non-parabolicity,
valley splitting
» Local (dis)order, strain and
orientation
Why can’t we scale planar Si devices forever?
Scaling Challenges and Issues
Material Problem
Structural Problem
Power Problem
Si NMOS
Velocity Saturation
Intel Single-Gate SOI
A. Khakifirooz et al., TED 55, 1391 (2008)
R. Chau et al., DRC, (2003)
Performance Limitation Turn ON/OFF Limitation
• Strain Engineering
• New Materials with
higher Mobility
Gerhard Klimeck
• Better Dielectrics
• New Structures with
better Channel Control
W. Haensch et al., IBM J. Res. Dev. 50, 339 (06)
Heat Dissipation
• Supply Voltage Scaling
• New Architectures with
steeper sub-Vth Slopes
P. Hashemi et al., EDL 30, 401 (2009)
L. Tapasztó et al., Nature Nano. 3, 397 (2008)
Graphene Nanoribbon
GAA Nanowire FETs
Search for the Next Generation Switch
What are the potential solutions?
III-V MOSFETs
Tunneling FETs
Y.Q. Wu et al., EDL 30, 700 (2009)
Gerhard Klimeck
W.Y. Choi et al., EDL 28, 743 (2007)
Design1
Physics-based Computer Aided Design (CAD)
Principle and Requirement
1.5
Design1
1
Design2
0.5
Design2
OMEN
CAD
Design3
0
ION (mA/μm)
…
100
Design1
50
Design2
Design3
Tool Features:
DesignN
Design3
• Specifically dedicated to nanoelectronic devices
=> beyond drift-diffusion and MC
• One single simulation engine
• One single set of approximations
• User friendly, fast, reliable
0
SS (mV/dec)
Gerhard Klimeck
…
150
Design1
100
Design2
50
Design3
0
DIBL (mV/V)
…
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
Quantum Transport far from Equilibrium
Macroscopic
dimensions
Law of Equilibrium :
Non-Equilibrium
Quantum
  exp (H
 N) /kT
Statistical
Mechanics
Atomic
dimensions

Drift /
Diffusion
s
Boltzmann
Transport
1
Non-Equilibrium
Which
Green
Functions
Formalism?
S
SILICON
VG
Gerhard Klimeck
I

 1

D
S
VD
Supriyo Datta
VG
I

2

D
INSULATOR

VD
2
H
From NEMO 1-D to OMEN
OMEN
(i)
(j)
GAA NW
Id-Vgs
Electron
Density
(k)
Features:
• 3D, Atomistic, and Full-Band Quantum Transport Simulator
• 4 Levels of Parallelism (V, k, E, and DD)
Gerhard Klimeck
(l)
What is OMEN?
Multidisciplinary Effort: PHYS – EE - HPC
Device Engineering
Physical Models
• Explore, Understand, Explain, • 3D Quantum Transport Solver
Optimize Novel Designs
• Accurate Representation of the
• Predict Device Performances
Semiconductor Properties
• Predict Eventual Deficiencies • Atomistic Description of Devices
Before Fabrication
• Ballistic and Dissipative
OMEN
• Accelerate Simulation Time
• Investigate New Phenomena
at the Nanometer Scale
• Move Hero Experiments to a
Day-to-Day Basis
Efficient Parallel Computing
Gerhard Klimeck
GAA NW
Electron
Density
Id-Vgs
Basic Device
Equations
OMEN Simulation
Approaches
Steady-State 1D/2D/3D Schrödinger Equation
H | ψE > = E | ψE >
Tight-Binding Ansatz for the Wave Function
∑ Cij(E,kt)Φσ (r - Rijk)eik ·r
σ
< r | ψE > =
t t
σ,ijk,kt
Atomic Orbitals
py
dz2-r2
(E-H-ΣRB+ΣRS)·GR = I
G< = GR·(Σ<B+Σ<S)·GR†
s/s*
pz
Scattering
(NEGF)
Gerhard Klimeck
px
dzx
dyz
dxy
(E-H-ΣRB)·C = Inj
Ballistic
Source: Wikipedia
(Wave Function) dx2-y2
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
III-V HEMTs: a path towards III-V MOSFETs
Problem: Si material is becoming too slow!
Solution: Materials with higher mobility than Si (InGaAs)
• III-V HEMTs: Similar structure to MOSFETs, no high-κ dielectric layer
• For experimentalists: excellent to test performances of III-V channels
• For theorists: excellent to test simulation and physical models
D.H. Kim et al., EDL 29, 830 (2008)
Gerhard Klimeck
III-V HEMTs: Modeling Challenges
Gerhard Klimeck
DeviceGGeometry
G
Σ ,S
Extrinsic device
Lg
Drain
n+ Cap
Gate
InAs
InGaAs
δ-doped
layer
Drain
InAlAs
Source
ΣS, SS
Source
n+ Cap
InP etch stop
ΣD, SD
Objective:
• Simulation of III-V HEMTs as first step
towards III-V MOSFETs
• Comparison with experimental data
• Design device with scaled Lg
Approach:
• Multi-scale domain decomposition
• Strain and material parameter
extraction from large atomistic domain
• Ballistic transport (no scattering) in
the effective mass approximation on
a reduced domain
• Injection from the Source, Drain, and
Gate contacts
Results/Impact:
• Match experimental results for various
gate lengths (30, 40, 50 nm)
Ongoing Work
• Better description of S and D contacts
Simulation Domain:
Intrinsic Device
InP Substrate
Gate Leakage Modeling
(E-H- ΣS -ΣD- ΣG)·C = SS+SD+SG
III-V HEMTs: Modeling Challenges
InAs
Objective:
3 Steps Process
• Simulation of III-V HEMTs as first step 1. Construct structure atom-by-atom
towards III-V MOSFETs
• Comparison with experimental data
• Design device with scaled Lg
Approach:
• Multi-scale domain decomposition
2. Relax atom positions (strain, disorder)
• Strain and material parameter
extraction from large atomistic domain
• Ballistic transport (no scattering) in
the effective mass approximation on
a reduced domain
• Injection from the Source, Drain, and
Gate contacts
Results/Impact:
In0.52Al0.48As
InAs
• Match experimental results for various
gate lengths (30, 40, 50 nm)
Ongoing Work
3. Extract material parameters
• Better description of S and D contacts
mtrans=0.049m0, mconf=0.096m0
Gerhard Klimeck
III-V HEMTs: Comparison to Measurement
Important Metrics
Lg (nm)
30
40
50
S(mV/dec)
DIBL(mV/V)
ION/IOFF
Exp.
107
169
0.47x103
Sim.
105
145
0.61x103
Exp.
91
126
1.38x103
Sim.
89
99
1.86x103
Exp.
85
97
1.80x103
Sim.
89
91
1.85x103
Gerhard Klimeck
vinj(cm/s)
3x107
3.11x107
3.18x107
•
•
•
•
Conclusion:
Good agreement for all Lg’s
Much higher injection velocities
than Si @VDD=0.5 V
Next: optimization for MIT
Next: Contact Modeling and
MOSFET Scaling
What can be changed?
• Gate geometry
• Channel thickness: tInAs
• Insulator thickness: tins
Better control of
surface potential
• Metal work function
engineering: ΦM
Gate leakage reduction
and E-mode operation
Lg=20nm
Gate
ΦM
tins
In0.53Ga0.47As
InAs
Gerhard Klimeck
tInAs
Drain
Source
In0.52Al0.48As
Parameters and Performances Summary
(1) Gate
geometry
(2) Channel
thickness
Improved gate control
• Lower SS
• higher ION/IOFF
(3) Insulator
thickness
Higher gate leakage
• Higher SS
• Lower ION/IOFF
SS
3
2
Gate leakage reduction
• Lower SS
• Higher ION/IOFF
ION/IOFF
1
Lg=20nm
(4) Metal work
function
4
4
1 2
3
Gerhard Klimeck
III-V HEMTs: Gate Length Scaling Lg=20 nm
• Channel Thickness Scaling: tInAs
• Insulator Thickness Scaling: tins
• Metal Work Function Engineering: ΦM
Better Control of
Surface Potential
Gate Leakage Reduction
Lg=20nm
Gate
Source
In0.53Ga0.47As
tInAs
InAs
In0.53Ga0.47As
tins
Drain
ΦM
In0.52Al0.48As
In0.52Al0.48As
Next Step: Scaling of III-V MOSFETs
Gerhard Klimeck
HEMT Simulator on nanoHUB.org
OMEN_FET:
• HEMTs, Single- and Double-Gate
devices
• Electron transport in Si and III-V
• Current Flow Visualization
http://nanoHUB.org/tools/omenhfet
Run your own simulations!
Gerhard Klimeck
Demo Flow>>
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
MOSFET vs TFET: Injection Mechanism
Problem with VDD Scaling:
• Subthreshold Swing (SS) limited
to 60 mV/dec
• Large ION/IOFF ratio => large VDD
• High Power Consumption
• VDD scaling not possible:
• either increase of IOFF
• or decreases of ION
ON
VDD
Hot Injection
OFF
ON
Solution: BTB Tunneling
•
•
•
•
No lower limit on the SS
Low Power Consumption
Various designs and materials
Biggest Challenges:
High ION
Steep SS
Low IOFF
Gerhard Klimeck
VDD
Cold Injection
OFF
ON
TFET: Open Questions
Assumptions:
• Any semiconductor material (Si,
Ge, C, InAs, InSb, InAs/GaSb)
equally viable
Graphene (C)
• Aim for 8-10nm technology
Tunable BG
• Aim for CMOS augmentation Symmetric BS
• Aim for low power
QW
GaSb
Open Questions
•
•
•
•
Which geometry: SG, DG, GAA?
Doping profiles?
Lateral or Vertical Tunneling?
Phonons – energy loss
Biggest Challenges:
High ION
Steep SS
Low IOFF
Gerhard Klimeck
InSb
Eg=0.169eV
(Bulk)
GNR
SingleGate
Broken Gap
Heterostructure
InAs 150 meV
Gate
Gate Oxide
N
N+
P+ Source
Buried Oxide
N+
DoubleGate
GateAllAround
Lateral TFETs: Influence of Body Thickness
Lg=20nm
Gate
InAs
tbody
Gate Oxide
P+ Source
5e19 cm-3
20nm
ΨS
Intrinsic
20nm
N+ Drain
5e19 cm-3
20nm
Buried Oxide
SS = ∂Vgs/∂log10Id = ∂Vgs/∂ΨS·SSint
Body Thickness Variation (Lg=20nm)
• Poor electrostatic for tbody>4nm
• SS below 60 mV/dec for tbody<4nm
• Low ON-Current despite highly and
abruptly doped source
Gerhard Klimeck
TFETs: InSb Devices
•Maximum Current of 330 μA/μm for DG UTB @ VDD=0.5 V
•SS below 60 mV/dec: GAA (9.2) < DG (20) < SG (34)
•Band Gap increase due to quantization
Gerhard Klimeck
Lateral TFETs: Influence of Source Doping
BTBT
•Assumption: abrupt
doping at s-c interface
•Assumption: high source
doping concentration
•Both conditions necessary
Gerhard Klimeck
•High Tunneling Current
=> Large NA
•Technology Limitation
(hard to fabricate abrupt
junction with high NA)
TFETs: Carbon-based Devices
Gate-Fringing Field
Eg
Eg=0.25eV
•Maximum Current of 320 μA/μm for SG GNR @ VDD=0.2 V
•Excellent electrostatic control in all cases => steep SS
•Strong influence of Gate-Fringing Field
Gerhard Klimeck
TFETs: Limitations of Graphene Nanoribbons
Gerhard Klimeck
TFETs: Broken-Gap Heterostructure Devices
•Maximum Current of 900 μA/μm for DG UTB @ VDD=0.5 V
•SS below 60 mV/dec: GAA (7) < DG (11) < SG (17)
•Band Gap increase due to quantization (especially InAs)
Gerhard Klimeck
Lateral TFETs: InSb vs GaSb-InAs BG
•InSb: maximum current of 330 μA/μm @ VDD=0.5 V
•GaSb-InAs: maximum current of 900 μA/μm @ VDD=0.5 V
•Assumptions: large source doping (NA=4e19 cm-3) and
abrupt source-channel interface
GaSb-InAs
InSb
Gerhard Klimeck
Gate
Gate Oxide
N+ Drain
P+ Source
Intrinsic
Buried Oxide
Gate
Gate Oxide
N+ Drain
P+ Source
Buried Oxide
Source: Chenming Hu, Green Transistor as a solution
to the IC power crisis.
Gerhard Klimeck
Lg=40nm
1E-06
1E-08
1E-10
0.0
N+ Pocket
N
Drain Current, ID (A/µm)
Lateral vs Vertical TFETs:
Influence of the Tunneling Area
1E-02
Eg=0.36eV, Vdd=0.2V ION
I
1E-04OFF
I
Eg=0.69eV, Vdd=0.5V
IOFF
Eg=1.1eV, Vdd=1V
C. Hu et al, 2008 VLSI-TSA, p. 14 (2008)
0.2
0.4
0.6
0.8
Gate Voltage, VGS (V)
1.0
InAs
InAsVertical
VerticalTFET
TFETSim.
Simulation
with OMEN
@ UCB
• •Non-equilibrium
Drift-Diffusion and
FB quantum
WKB approximation
transport
• •Tunneling
Tunnelingpresent
only in everywhere:
pre-defined regions,
vertical,
horizontal,
along mesh
diagonal,…
lines, generally no angle
• •High
HighION
ION
, but
andhigh
lowIIOFF
predicted
OFFtoo
ON
Vertical TFET: Spatial Current Distributions
n+ Pocket
n+ Drain
n+ Pocket
n+ Drain
p+ Source
p+ Source
Vertical TFFET ON-Current
Vertical TFET OFF-Current
• Quasi-vertical tunneling between the • Quasi-lateral tunneling between p+
n++ Pocket and the p+ Source close to Source and n+ Drain close to the
the Gate
Buried Oxide
• Non-homogeneous tunneling, 2 main • No electrostatic control over the
tunneling channels
tunneling region
Gerhard Klimeck
Vertical TFET: OFF-State Current
Gate
Gate
Gate Oxide
Gate Oxide
N+ Pocket
P+ Source
P+ Source
N
Intrinsic/do
ped
N+ Drain
N+ Drain
Buried Oxide
Buried Oxide
EC Source
• Region below the Pocket &
p-i-n lateral TFET similar
• No electrostatic control
away from the gate
• Source-to-drain tunneling
leakage path
Gerhard Klimeck
EV
BTBT
Drain
Improved Design
Gate
ION
Gate Oxide
IOFF
N+ Pocket
P+ Source
N
N+ Drain
Buried Oxide
Gate
Results:
Gate Oxide
N+ Pocket
N
N+ Drain
P+ Source
Push up
the oxide
Buried Oxide
• decrease of the OFF-current by
several orders of magnitude
• further optimizations required to
obtain high performance device (not
included in this patent form)
35
Provisional patent filed a year ago, full patent filed now
Gerhard Klimeck
Improved Design
Vertical
TFET Conclusions
Gate
Gate Oxide
•Vertical
TFET with structural problem
N N+ Drain
N+ Pocket
I
=>
lateral
tunneling
leakage
P+ Source
OFF
Push up
the oxide
•Commercial TCAD unable to predict
Buried Oxide
internal deficiency
Technical Solution:
Results:
=> misleading consequences
• push up the buried oxide below the
drain contact to block the lateral
source-to-drain tunneling path
• alternative: use of a large band gap
material on the drain side to obtain
the same blocking effect
• decrease of the OFF-current by
several orders of magnitude
• further optimizations required to
obtain high performance device (not
included in this patent form)
•OMEN with global tunneling model as
a more accurate solution
=> save time and money
36
Provisional patent filed a year ago, full patent filed now
Gerhard Klimeck
TFETs: Phonon-Assisted Tunneling
Simulation of Si Nanowire TFETs:
Effects of Electron-Phonon Scattering
Gerhard Klimeck
Objective:
• Simulation of Phonon-Assisted
Tunneling (PAT) in TFETs
• Design Si-Ge heterostructure
devices for high ON-currents
Approach:
• Atomistic and full-band model
• NEGF up to self-consistent
Born approximation
• Confined phonon dispersion
Result/Impact:
• First demonstration of PAT in
3-D nanowires with global
tunneling model
• Si, Ge, and InAs nanowire
TFETs simulated
Ongoing Work
• Same capability for UTB
Ballisticity of Si NW FETs
Objective:
x=<100>
•Electron-Phonon in Si NW FETs,
extract vinj, μPH, and B factor
Approach:
•Accurate description of the
semiconductor material properties
d=3nm
•Atomistic Representation of the NWs
•Quantized phonon dispersion
•Quantum transport with NEGF
Si Bandstructure
Results and Impacts:
•Reduction of the drain current and
injection velocity, modification of the
electrostatics
•First demonstration of FB + El-Ph
Ongoing Work:
•Mobility extraction in n/p NW FET
•Experimental data to verify the model
Gerhard Klimeck
Lg=15nm
Phonon Dispersion
Acoustic
Branches
m*=0.29m0
Ballisticity of Si NW FETs
Objective:
•Electron-Phonon in Si NW FETs,
extract vinj, μPH, and B factor
Approach:
•Accurate description of the
semiconductor material properties
•Atomistic Representation of the NWs
•Quantized phonon dispersion
•Quantum transport with NEGF
Results and Impacts:
•Reduction of the drain current and
injection velocity, modification of the
electrostatics
•First demonstration of FB + El-Ph
Ongoing Work:
•Mobility extraction in n/p NW FET
•Experimental data to verify the model
Gerhard Klimeck
vinj
vinj=1.3e7 cm/s
vinj=0.9e7 cm/s
vinj
B=70%
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
Transport spectroscopy of a single gated donor atom
Delft, IMEC, Melbourne, Purdue
Objective:
• Support single impurity spectroscopy
Approach:
• Experiments & NEMO3D
Results / Impact:
• Joint publications 2 experimental & 2 theory
groups (Lansbergen et al)
• Nature Physics,
pMetrology
656 (2008) with multimillion atom simulations
Gerhard V4,
Klimeck
Stark Effect in donor-interface Well
Dependence on donor type, depth and electric field
Si:As
(D=4.3 nm)
Si:As
(D=15 nm)
Si:P
(D=4.3 nm)
Symmetry Transition of the GS at D=4.3 nm (Si:As)
E=0 MV/m
Gerhard Klimeck
E=25 MV/m
E=40 MV/m
42
Stark Effect in donor-interface Well
Dependence on donor type, depth and electric field
Si:As
(D=4.3 nm)
Symmetry Transition of the GS at D=4.3 nm (Si:As)
E=0 MV/m
E=25 MV/m
E=40 MV/m
Must
have
excited states
under
realistic
Gerhard
Klimeck
Lansbergen,
Rahman,
Wellard,
et al. gate potentials!
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
Towards Peta-Scale Device Simulations
What is the originality of the approach?
Atomistic Schrödinger Equation with Open Boundary Conditions
Ballistic Transport, NA atoms per cross section, tb orbitals
“Golden” Standard
1. Open Boundary Conditions
New Approach in OMEN
1. Open Boundary Conditions
a
a
(a) Iterative Methods (Sancho-Rubio)
Normal Eigenvalue Problem
(a) (E - H - t10 ∙
(a) NBC = NA•tB
(a)
gR ∙ t01) ∙ gR = I
a
(b) Generalized Eigenvalue Problem
(b) A•Ф = exp(i•k•Δ)•B•Ф
(b) NBC = 2•NA•tB
2. Schrödinger Equation
(a)
a
M•Ф = 1/(exp(i•k•Δ)-1)•Ф
NBC ≤ NA•tB
(a)
Reduced Size Problem
Gain Factor: 10-100 in 3-D
a
2. Schrödinger Equation
(a)
a
(E-H-ΣB)·GR = I
(a)
Recursive Green’s Function (RGF) Algorithm
Block-tridiagonal Matrices
Gerhard Klimeck
(E-H-ΣB)·C = S
(a)
Sparse Linear Systems of Equations
No Restrictions on the Matrices
Gain Factor: 5-20 in 3-D
Towards Peta-Scale Device Simulations
Example: 3-D Nanowire
NAC = 265 atoms per wire unit cell
NUC = 64 unit cells
NUC =16,960 atoms in the nanowire
3nm
L=35nm
sp3d5s* tight-binding model (tb=10)
typically: 1,000-1,500 energies
Solution Time per Energy Point
“Golden” Standard
New Approach in OMEN
3nm
Speed-Up
1. OBC (Sancho-Rubio NBC=2650)
1. 36x
OBC (EV Problem NBC=1330)
tOBC = 831 sec (60%)
tOBC = 23.1 sec (30%)
2. Schrödinger Equation (RGF)Speed-Up
2. 10x
Schrödinger Equation (Sparse LSE)
tSE = 551 sec (40%) on 1 cores
tSE = 54.4 sec (70%) on 1 cores
Difficult to parallelize
tSE = 9.65 sec on 8 cores (5.6x faster)
Speed-Up 18x
3. Total: 1382 sec per energy on 1 core
Gerhard Klimeck
3. Total: 77.5 sec per energy on 1 core
Gerhard Klimeck
MPI
Objective:
• NEGF with Atomistic Basis
Approach:
• Multi-Level parallelism
• Voltage
• Momentum
• Energy
• Space
• Mixed MPI / OpenMP
• Dynamic load balancing
in double integral
• Computational Interleaving
• Leverage of existing linear solvers
(Pardiso, MUMPs, SuperLU,
Umfpack, …)
• Novel:
• Development of new solvers
(Basis Compression Algorithm)
OpenMP
OMEN Parallel Architecture
Quad-Level Parallelisation Scheme
Tested on multiple platforms
Towards Peta-Scale Device Simulations
OMEN Scaling to 222,720 Cores
Result:
• Highly efficient parallel
algorithm, stressing the
most advanced
resources available today
• Implementation and test of
electron-phonon scattering
Impact:
• Move from nano-science
to nanodevice engineering
in minutes
• Unprecedented insight
into atomistic device
simulation
• One of the 10-15 codes
capable of running on
Jaguar full capability
• Close to peta-scale
performances without any
external advice or tuning
Gerhard Klimeck
Computational Load
Ballistic vs. Electron-Phonon Scattering
Ballistic Transport:
Ideal Scaling 222,720 cores
• >90% parallel efficiency on 95k cores
• >860 TFlop/s on 222k cores
Gerhard Klimeck
Transport with Scattering:
>100-1,000x more intensive!
Much more communication!
1 bias point (20 for 222,720 cores)
• 58% parallel efficiency on 95k cores
• 142 TFlop/s on 95k cores
U.S. Science and Engineering
Computational Resources
Ranger@TACC
~64,000 cores
SUN / AMD cores
Gerhard Klimeck
Jaguar@ORNL
~225,000 cores
Cray XT5 / AMD cores
Kraken@NICS
~95,000 cores
Cray XT4 / AMD cores
Overview
•Why Physics-Based Device Modeling?
From Moore’s Law to NEMO/OMEN
• Simulation Approach
• Application to Nanoscale Device
III-V High Electron Mobility Transistors
Band-to-Band Tunneling Transistors
Single impurity devices
• Towards Peta-Scale Device Simulations
•Conclusions
Gerhard Klimeck
NEMO/OMEN =
New Physics-Based TCAD
OMEN/NEMO Simulation Approach
•
•
•
•
3D, full-band, atomistic, quantum transport
UTB, NW, or HEMT structures BTBT
Electron-phonon scattering
Single impurity modeling
Outlook and Near Term Challenges
• explore design space for nano-scaled FETs
sizes/materials/doping
• Explore doping effects, explicit impurities,
bandgap narrowing
• Aid experiments
OMEN/NEMO on
nanoHUB.org
Over 5,000 users
Gerhard Klimeck
Intel TCAD
group is using OMEN now! IBM expressed interest
Gerhard Klimeck
Band-to-Band Tunneling Transistors
Problem: Increase in power consumption of MOSFETs
W. Haensch et al., IBM J. Res. Dev. 50, 339 (06)
2
• Active power: ~VDD
• Passive sub-Vth leakage power
• Passive gate leakage power
Gerhard Klimeck
Reduction of Active Power:
Scaling of VDD,
but it is slowing down!
Basic Device Equations
1D/2D/3D
Schrödinger
Equation On-Site
Hamiltonian
(Device Description,
Energy,
H | ψNeighbor
> = Coupling)
E|ψ >
H
E
E
ΣRB, Σ<B, Linear
Inj Open
Boundary
(Connection
Expansion
of Conditions
the Wave Function
to Contacts) σ
<<Sr | ψE > =
ΣRS, Σ
∑ Cij(E,kt)Φσ (r - Rijk)eik ·r
Scattering
(Interactions with
σ,ijk,kSelf-Energies
t
Phonons, Photons, Impurities, …)
(E-H-ΣRB+ΣRS)·GR = I
G< = GR·(Σ<B+Σ<S)·GR†
Scattering (NEGF)
Gerhard Klimeck
t t
(E-H-ΣRB)·C = Inj
Ballistic
(Wave Function)
How does it work?
Structure Generator
Loop over
Bias Points
Hamiltonian Generator
Loop over
Energy/Momentum
Boundary Conditions
Poisson Equation
Transport/Scattering
No
Electrostatics
Gerhard Klimeck
OK?
Yes
Carrier Density
Current
Electron-Phonon Scattering: Principle
Electron-Phonon Scattering:
•coupling between different Energies and
Momenta
•More difficult to parallelize than ballistic
Gerhard Klimeck
Electron-Phonon Scattering: Scaling Performances
Scaling on 3,276 up to 95,256 cores
• 1 bias point (20 for 222,720 cores)
• 58% parallel efficiency on 95k cores
• 142 TFlop/s on 95k cores
Gerhard Klimeck
Time Decomposition up to 95k cores
• calculation of self-energy scales well
• calculation of Green’s functions idem
• communication time dominates on 95k