Transcript Les instruccions en assemblador dels PIC

* Pepe

PICmicro
Sagitrón Jornadas MMIV / 2-INSTR / 1 de 28
© 2002 Microchip Technology Incorporated. All Rights Reserved.
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RISC
•
•
•
•
12-bit core
14-bit core
16-bit core
16-bit enh. core









33 instructions
35 instructions
58 instructions
72+4 instructions
Easy to learn
High compaction
Very powerful single-word instructions
All single- cycle except program branches
Upward compatibility of instructions
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Instrucciones PIC16C5X (33):
Byte-Oriented Operations
Bit-Oriented Operations
No Operation
NOP
Move W to f
MOVWF f
Clear W
CLRW Clear f
CLRF f
Subtract W from f
SUBWF f,d
Decrement f
DECF f,d
Inclusive OR W and f
IORWF f,d
AND W and f
ANDWF f,d
Exclusive OR W and f XORWF f,d
Add W and f
ADDWF f,d
Move f
MOVF f,d
Complement f
COMF f,d
Increment f
INCF
f,d
Decrement f, skip if zero DECFSZf,d
Rotate right f
RRF
f,d
Rotate left f
RLF
f,d
Swap halves f
SWAPF f,d
Increment f, skip if zero INCFSZ f,d
Bit clear f
Bit set f
Bit test f, skip if clear
Bit test f, skip if set
f,b
f,b
f,b
f,b
Literal and Control Operations
Go into standby mode SLEEP Clear Watchdog Timer CLRWDT Return, place Literal W RETLW k
Option
OPTION Tris Port
TRISF
f
Call Subroutine
CALL
a
GOTO
a
Go to address
Move Literal to W
MOVLW k
AND Literal W
ANDLW k
Inclusive OR Literal W IORLW k
Exclusive OR Literal W XORLW k
f = file register address
d = destination select
a = program address
b = bit
k = literal
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BCF
BSF
BTFSC
BTFSS
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Codificación instrucciones 12-bit
Byte Oriented Operations
OP CODE
d
f f f f f
Bit Oriented Operations
OP CODE
b b b
f f f f f
Literal Operations
OP CODE
k k k k k k k k
PC call and goto
OP CODE x a a a a a a a a
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Mapa de Registros PIC16C5X
00
0
F
10
1
F
*
Indirect addr*
TMR0
PCL
STATUS
FSR
PORT A
PORT B
PORT C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bank 0
X
X
Bank 1
X
X
Bank 2
X
X
Bank
3
Not a physical register
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Directo PIC16C5X
• 5-bit direct address from the instruction
• 2-bit from FSR register
FSR Register
12-bit Instruction
RA1RA0
OP CODE
2-bits From
FSR
Register
f
f
f
f
f
5-bits From Instruction Word
RA1 RA0 f
f
f
f
f
Effective 7-bit Register Address
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Indirecto PIC16C5X
• 5-bit indirect address from the FSR (File Select Register).
• 2-bit from FSR register
FSR Register
File Select Register
RA1RA0
f
2-bits From
FSR
Register
f
f
f
f
5-bits From FSR
RA1 RA0 f
f
f
f
f
Effective 7-bit Register Address
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Indirecto PIC16C5X

Clear all RAM locations from 0x10 to 0x1F.
 Indirect address is loaded into FSR.
 Every time INDF is used as operand,
register pointed to by FSR is actually used.
Data Memory
00h
INDF
04h FSR = 10h
10h 0000 0000
movlw
0x10
movwf
FSR
LOOP clrf
INDF
incf
FSR,F
btfsc
FSR,4
goto
LOOP
<next instruction>
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1Fh XXXX XXXX
Sagitrón Jornadas MMIV / 2-INSTR / 8
© 2002 Microchip Technology Incorporated. All Rights Reserved.
GOTO: Salto Incondicional PIC16C5X
STATUS
• GOTO: 9-bit destination address
is loaded into PC <8:0>.
The upper 2-bit PC <10:9> are
loaded from STATUS <6:5>
allowing 4x512 (2K) addressing
range.
xppxxxxx
PCL
p p
a
aaaaaaaa
GOTO
101 a
aaaaaaaa
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CALL: Llamada a Rutina PIC16C5X
STATUS
• CALL: 8-bit destination address
is loaded into PC <7:0>.
PC <8> is forced to “0”.
The upper 2-bit PC <10:9> are
loaded from STATUS <6:5>
allowing lower half of 4x512
(1K) addressing range.
It means that all subrutine entry
must be located in the lower half
of any page.
xppxxxxx
PCL
p p
0
aaaaaaaa
CALL
100 1
aaaaaaaa
• RETLW: PC <10:0> is loaded from
the top of the stack.
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Sagitrón Jornadas MMIV / 2-INSTR / 10
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Escritura en el PC: PIC16C5X
STATUS
• WRITE to PC: When the PC is the
destination of any instruction, the
computed 8-bit value will be loaded
into PC <7:0>.
PC <8> is forced to “0”.
The upper 2-bit PC <10:9> are
loaded from STATUS <6:5>
allowing lower half of 4x512
(1K) addressing range.
It means that any computed jump
must be located in the lower half
of any page.
xppxxxxx
PCL
p p
0
aaaaaaaa
WRITE to PC
dddddddd
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Instrucciones PIC16FXXX (35):
Byte-Oriented Operations
Bit-Oriented Operations
No Operation
NOP
Move W to f
MOVWF f
Clear W
CLRW
Clear f
CLRF f
Subtract W from f
SUBWF f,d
Decrement f
DECF f,d
Inclusive OR W and f
IORWF f,d
AND W and f
ANDWF f,d
Exclusive OR W and f XORWF f,d
Add W and f
ADDWF f,d
Move f
MOVF f,d
Complement f
COMF f,d
f,d
Increment f
INCF
Decrement f, skip if zero DECFSZf,d
f,d
Rotate right f
RRF
f,d
Rotate left f
RLF
Swap halves f
SWAPF f,d
Increment f, skip if zero INCFSZ f,d
Bit clear f
Bit set f
Bit test f, skip if clear
Bit test f, skip if set
f = file register address
d = destination select
a = program address
b = bit
k = literal
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BCF
BSF
BTFSC
BTFSS
f,b
f,b
f,b
f,b
Literal and Control Operations
Go into standby mode
Clear Watchdog Timer
Return, place Literal W
Return from interrupt
Return
Call Subroutine
Go to address
Move Literal to W
Add Literal to W
Subtract Literal from W
AND Literal W
Inclusive OR Literal W
Exclusive OR Literal W
SLEEP
CLRWDT
RETLW
RETFIE
RETURN
CALL
GOTO
MOVLW
ADDLW
SUBLW
ANDLW
IORLW
XORLW
k
a
a
k
k
k
k
k
k
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
Codificación instrucciones 14-bit
Byte Oriented Operations
OP CODE
d
f f f f f f f
Bit Oriented Operations
OP CODE
b b b
f f f f f f f
Literal Operations
OP CODE
k k k k k k k k
PC call and goto
OP CODE a a a a a a a a a a a
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Sagitrón Jornadas MMIV / 2-INSTR / 13
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Mapa de Registros PIC16FXXX
00
Indirect addr*
TMR0
PCL
STATUS
FSR
PORT A
PORT B
X
X
X
PCLATH
INTCON
X
X
X
Indirect addr*
OPTION
PCL
STATUS
FSR
TRIS A
TRIS B
X
X
X
PCLATH
INTCON
X
X
X
FF
7F
Bank 0
*
80
Bank 1
Bank 2
Bank 3
Not a physical register
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Sagitrón Jornadas MMIV / 2-INSTR / 14
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Directo PIC16FXXX
• 7-bit direct address from the instruction
• 2-bit from STATUS register
STATUS Register
14-bit Instruction
IRP RP1 RP0 TO PD Z DC C
2-bits From
STATUS
Register
RP1 RP0 f
OP CODE
f
f
f
f
f
f
f
7-bits From Instruction Word
f
f
f
f
f
f
Effective 9-bit Register Address
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Sagitrón Jornadas MMIV / 2-INSTR / 15
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Indirecto PIC16FXXX
•
•
8-bit indirect address from the FSR (File Select Register).
1-bit from STATUS register.
STATUS Register
8-bit FSR Register
IRP RP1 RP0 TO PD Z DC C
1-bit From
STATUS
Register
f
f
f
f
f
f
f
f
8-bits From FSR
IRP f
f
f
f
f
f
f
f
Effective 9-bit Register Address
Sagitrón Jornadas MMIV / 2-INSTR / 16
© 2002 Microchip Technology Incorporated. All Rights Reserved.
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Direccionamiento Indirecto PIC16FXXX

Clear all RAM locations from 0x20 to 0x7F.
 Indirect address is loaded into FSR.
 Every time INDF is used as operand,
register pointed to by FSR is actually used.
Data Memory
00h
INDF
04h FSR = 20h
20h 0000 0000
movlw
0x20
movwf
FSR
LOOP clrf
INDF
incf
FSR,F
btfss
FSR,7
goto
LOOP
<next instruction>
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7Fh 0000 0000
Sagitrón Jornadas MMIV / 2-INSTR / 17
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Inmediato PIC16FXXX


8-bit constant (literal) value included in
instruction word.
Used by literal instructions such as
movlw, addlw, retlw, etc.
14-bit Instruction for Literal Instructions
OP CODE
k k k k k k k k
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Sagitrón Jornadas MMIV / 2-INSTR / 18
© 2002 Microchip Technology Incorporated. All Rights Reserved.
GOTO: Salto Incondicional PIC16FXXX
• GOTO: 11-bit destination address
is loaded into PC <10:0>.
The upper 2-bit PC <12:11> are
loaded from PCLATH <4:3>
allowing 4x2K (8K) addressing
range.
OP CODE a a a a a a a a a a a
p p a a a a a a a a a a a
Program Counter
x x x p p x x x
PCLATH
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© 2002 Microchip Technology Incorporated. All Rights Reserved.
CALL: Llamada a Rutina PIC16FXXX
• CALL: 11-bit destination address
is loaded into PC <10:0>.
The upper 2-bit PC <12:11> are
loaded from PCLATH <4:3>
allowing 4x2K (8K) addressing
range.
OP CODE a a a a a a a a a a a
• RETLW,
RETURN and
p p a a a a a a a a a a a
RETFIE:
PC <12:0> is loaded
Program Counter
from the top of the
stack. PCLATH is
unchanged.
x x x p p x x x
PCLATH
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Sagitrón Jornadas MMIV / 2-INSTR / 20
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Direccionamiento Relativo PC PIC16FXXX

Used to perform a computed goto by adding an offset
directly to the 13-bit Program Counter (8K addressing).
Internal Data Bus <8>
First write high byte to
PCLATH.
 Next write low byte to
PCL, this loads the entire
13-bit value to PC.
 Reading the PC
 Read low byte
from PCL
 PCLATH is NOT
loaded with
value from PCH

Sagitrón Jornadas MMIV / 2-INSTR / 21
5
PCLATH <5>
8
5
PCH <5>
PCL <8>
13-Bit Program Counter
© 2002 Microchip Technology Incorporated. All Rights Reserved.
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Instrucciones 12-bit < > 14-bit
• Do NOT use OPTION AND TRIS instructions
on 14 bit core devices.
• These Instructions are not in the 12 bit core:
ADDLW - Add literal k to contents of W register
SUBLW - Subtract W from Literal
RETURN - Return from subroutine
RETFIE - Return from interrupt subroutine
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Sagitrón Jornadas MMIV / 2-INSTR / 22
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Instrucciones PIC17CXXX (58): ...
Byte-Oriented Operations
Byte-Oriented Operations
No Operation
Clear f
Set f
Move W to f
Move f to p
Move p to f
Negate W
Complement f
AND W with f
Incl OR W with f
Excl OR W with f
Add W with f
Add W with f + CY
Sub W with f
Sub W with f + BW
Decimal Adjust W
Swap f
Multiply W with f
Decrement f
Decr f skip if ZR
Decr f skip if NZR
Increment f
Incr f skip if ZR
Incr f skip if NZR
Comp f-W skip if =
Comp f-W skip if >
Comp f-W skip if <
Test f skip if ZR
Rotate left f with CY
Rotate left f without CY
Rotate right f with CY
Rotate right f without CY
Table read
Table write
Table latch read
Table latch write
NOP
CLRF
f,s
SETF
f,s
MOVWF f
MOVFP f,p
MOVPF p,f
NEGW f,s
COMF
f,d
ANDWF f,d
IORWF f,d
XORWF f,d
ADDWF f,d
ADDWFC f,d
SUBWF f,d
SUBWFB f,d
DAW
f,s
SWAPF f,d
MULWF f
f / p = file / peripheral register address
d / s = destination select
a = program address
b = bit
k = literal
Sagitrón Jornadas MMIV / 2-INSTR / 23
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
CPFSEQ
CPFSGT
CPFSLT
TSTFSZ
RLCF
RLNCF
RRCF
RRNCF
TABLRD
TABLWT
TLRD
TLWT
t = Table latch high or low tranfer
i = Autoincrement pointer
© 2002 Microchip Technology Incorporated. All Rights Reserved.
* Pepe
f,d
f,d
f,d
f,d
f,d
f,d
f
f
f
f
f,d
f,d
f,d
f,d
t,i,f
t,i,f
t,f
t,f
... Instrucciones PIC17CXXX (58):
Bit-Oriented Operations
Bit clear f
Bit set f
Bit toggle f
Bit test skip 0
Bit test skip 1
Literal and Control Operations
BCF
BSF
BTG
BTFSC
BTFSS
f,b
f,b
f,b
f,b
f,b
f / p = file / peripheral register address
d / s = destination select
a = program address
b = bit
k = literal
Sagitrón Jornadas MMIV / 2-INSTR / 24
Move literal to W
Move literal low BSR
Move literal high BSR
AND literal with W
Incl OR literal with W
Excl OR literal with W
Add literal with W
Sub literal with W
Multiply Lit with W
Go to address
Subrutine call
Subrutine Long call
Return literal to W
Return subrutine
Return from int.
Clear Watchdog
Go to standby mode
MOVLW k
MOVLB k
MOVLR k
ANDLW k
IORLW k
XORLW k
ADDLW k
SUBLW k
MULLW k
GOTO
a
CALL
a
LCALL
a
RETLW k
RETURN RETFIE CLRWDT SLEEP
-
t = Table latch high or low tranfer
i = Autoincrement pointer
© 2002 Microchip Technology Incorporated. All Rights Reserved.
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Instrucciones PIC18FXXXX (76): ...
Byte-Oriented & Literal
Add literal with Wreg
Add Wreg with f
Add Wreg with f + carry
And literal with Wreg
And Wreg with f
Clear f
Complement f
Compare f with Wreg, skip if =
Compare f with Wreg, skip if >
Compare f with Wreg, skip if <
Decimal adjust Wreg
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if /0
Increment f
Increment f, Skip if 0
Increment f, Skip if /0
Inclusive OR literal with Wreg
Inclusive OR Wreg with f
Move literal to FSRx
f = file register address
n&p = program address
Sagitrón Jornadas MMIV / 2-INSTR / 25
ADDLW k
ADDWF f,d,a
ADDWFC f,d,a
ANDLW k
ANDWF f,d,a
CLRF
f,a
COMF
f,d,a
CPFSEQ f,a
CPFSGT f,a
CPFSLT f,a
DAW
DECF
f,d,a
DECFSZ f,d,a
DCFSNZ f,d,a
INCF
f,d,a
INCFSZ f,d,a
INFSNZ f,d,a
IORLW k
IORWF f,d,a
LFSR
x,k
Move f
Move fs(source) to fd(destin)
Move literal to BSR
Move literal to Wreg
Move Wreg to f
Multiply literal with Wreg
Multiply Wreg with f
Negate f
Rotate Left f through carry
Rotate Left f (no carry)
Rotate Right f through carry
Rotate Right f (no carry)
Set f
Subtract f from Wreg + borrow
Subtract Wreg from literal
Subtract Wreg from f
Subtract Wreg from f + borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR literal with Wreg
Exclusive OR Wreg with f
d = destination select
b = bit
k = literal
a = banck select
s = shadow reg.
© 2002 Microchip Technology Incorporated. All Rights Reserved.
MOVF
MOVFF
MOVLB
MOVLW
MOVWF
MULLW
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBLW
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORLW
XORWF
* Pepe
f,d,a
fs,fd
k
k
f,a
k
f,a
f,a
f,d,a
f,d,a
f,d,a
f,d,a
f,a
f,d,a
k
f,d,a
f,d,a
f,d,a
f,a
k
f,d,a
... Instrucciones PIC18FXXXX (76):
Control operations
Branch if carry
Branch if no carry
Branch if negative
Branch if no negative
Branch if overflow
Branch if no overflow
Branch if zero
Branch if no zero
Branch unconditionally
Go to address
Relative call
Call subroutine
Return from subroutine
Return with literal in Wreg
Return from interrupt enable
Pop top of return stack
Push top of return stack
No operation
No operation 2nd word
Clear watchdog timer
Change into standby mode
Software device reset
f = file register address
n&p = program address
Sagitrón Jornadas MMIV / 2-INSTR / 26
BC
BNC
BN
BNN
BOV
BNOV
BZ
BNZ
BRA
GOTO
RCALL
CALL
RETURN
RETLW
RETFIE
POP
PUSH
NOP
Bit-Oriented
n
n
n
n
n
n
n
n
n
p
n
p,s
s
k
s
Bit clear into f
Bit set into f
Bit toggle into f
Bit test f, skip if clear
Bit test f, skip if set
BCF
BSF
BTF
BTFSC
BTFSS
f,b,a
f,b,a
f,b,a
f,b,a
f,b,a
Data <==> Program Memory
Table read
Table read with pre-increment
Table read with post-increment
Table read with post-decrement
Table write
Table write with pre-increment
Table write with post-increment
Table write with post-decrement
CLRWDT
SLEEP
RESET
d = destination select
b = bit
k = literal
a = banck select
s = shadow reg.
© 2002 Microchip Technology Incorporated. All Rights Reserved.
TBLRD*
TBLRD+*
TBLRD*+
TBLRD*TBLWT*
TBLWT+*
TBLWT*+
TBLWT*-
* Pepe
Instrucciones Especiales de los PICs
CLRWDT
• CLRWDT: Watchdog timer and its postscaler are cleared.
/TO = 1 and /PD = 1
If WDT overflow resets the chip
CLRWDT
‘0’
Internal
free-running
RC
Oscillator
8-bit Ripple Counter
‘0’
Postscaler
Overflow
Resets
Chip
* Pepe
Sagitrón Jornadas MMIV / 2-INSTR / 27
© 2002 Microchip Technology Incorporated. All Rights Reserved.
Instrucciones Especiales de los PICs
SLEEP
• The processor can be put into a power-down mode by
executing the SLEEP instruction.
OSC1
SLEEP
Osc.
Disable
–
–
–
–
–
–
–
–
–
OSC2
System oscillator is stopped.
Processor status is maintained (static design).
I/O pins configured as output will continue to drive
Wake-up (WDT) and its postscaler are cleared.
/TO = 1 and /PD = 0.
Wake-up (WDT) timer continues to run, if enabled.
Minimal supply current is drawn - mostly due to leakage.
Power-Down Current: 0.1 - 3.5A typical.
Device remain in power down until any wake-up.
* Pepe
Sagitrón Jornadas MMIV / 2-INSTR / 28
© 2002 Microchip Technology Incorporated. All Rights Reserved.