Transcript Page 62 in Chassaing

Page 62 in Chassaing
;SINEALL.ASM - GENERATES A SINE WITH 4 POINTS USING AIC POLLING
.start ".text",0x809900
;starting addr for code
.start ".data",0x809c00
;starting addr for data
.data
;data section
PBASE
.word
808000h
;peripheral base address
SETSP
.word
0E970300h
;serial port set-up data
ATABLE
.word
AICSEC
;SP0 AIC init table addr
AICSEC
.word
162Ch,1h,4892h,67h
;Fs = 8 kHz
SINE_ADDR
.word
SINE_VAL
;address of sine values
.brstart "SINE_BUFF", 8
;size of sine table
SINE_VAL
.word 0,1000,0,-1000
;sine values
LENGTH
.set
;length of circular buffer
4
.entry BEGIN
;start of code
.text
;assemble into text section
The .start directive links the section name to start at location
address. For the section to have a valid starting address, the .start
statement for the section must precede the .text, .data, or .sect
directive that defines the section name.
.start directive
defines the starting
address of the section
.start
".text",0x809900
;starting addr for code
.start
".data",0x809c00
;starting addr for data
defines the section
So the program (text) starts at location 809900 and the the data starts at
location 809c00.
DATA
PBASE
809c00
808000
STEPSP
809c01
0E970300
ATABLE
809c02
809c03
AICSEC
809c03
162c
809c04
0001
809c05
4892
809c06
67
SINE_ADDR
SINE_VAL
.word SINE_VAL
;address of sine values
.brstart "SINE_BUFF", 8
;size of sine table
.word 0,1000,0,-1000
;sine values
SINE_VAL
809C08
The .bstart directive aligns the section
name to the next 2n address boundary
following the current section.
0
1000
809C09
-1000
0
Beginning address of
the program
809900
BEGIN
LDP AICSEC
LDI @PBASE,AR0
LDI 1h,R0
STI R0,*+AR0(28h)
LDI 03C1h,R0
STI R0,*+AR0(20h)
LDI 62h,IOF
LDI @ATABLE,AR1
;init to data page 128
;AR0=peripheral base address
;Timer CLK=H1/2*(AIC master CLK)
;timer period reg(TCLK0=6.25MHZ)
;to init timer global register
;reset timer
;AIC reset = 0
;AR1=AIC init data
DIRECT ADDRESSING
page 255
page 254
256 Pages
page
page 3
page 2
page 1
0000
page 0
64K page
The data address is formed by the
concantenation of the eight least
significant bits of the data page
pointer (DP) with the 16 least
significant bits of the instruction
word.
This results in 256 pages of memory
with 64K words per page. The DP
must contain the proper value before
using direct addressing.
FFFF
DP
16 bits of operand
AR0 
LDI
@PBASE,AR0 ;AR0=peripheral base address
AR0
AR0 

AR0 + 28 
LDI
STI
1h,R0
R0,*+AR0(28h)
;Timer CLK=H1/2*(AIC master CLK)
;timer period reg(TCLK0=6.25MHZ)
As shown in the previous slide, the timer (TCLK0) signal is
connected to the AIC’s master clock (MCLK) signal. The
MCLK signal drives all the key logic signals of the AIC, such as
the shift clock, the switched-capacitor filter clocks, and the A/D
and D/A timing signals. The timer pulses the TCLK0 signal
whenever the timer counter register (0x0080 8024) counts up to
the timer period register (0x0080 8028) value. Then the timer
counter register resets to zero and repeats.
AR0 
LDI
STI
03C1h, R0
R0, *+AR0(20h)
;to init timer global register
;reset timer
03C1
Bits
0
1
2
3
4-5
6
7
8
9
10
11
12-31
Status
1
0
0
Read-only
0
1
1
1
1
0
Read-only
0
Signal Name
FUNC
I/O
DATAOUT
DATAIN
Reserved
GO
HLD
C/P
CLKSRC
INV
TSTAT
Reserved
Setting
TCKL0 is configured as a timer pin
Unused
Unused
Unused
Unused
Starts Timer running
Timer not held
Timer in clock mode
Internal clock source
Clock output active high
Unused
Unused
AR0 
LDI
LDI
RPTS
NOP
62h,IOF
@ATABLE,AR1
99
;AIC reset = 0
;AR1=AIC init data
;repeat next instr 100 times
;keep IOF low for a while
IOF (IO Flag Register)
31-16
15-12
11-8
xx
xx
xx
7
6
5
INXF1 OUTXF1 I/OFX1
4
xx
3
2
1
INXF0 OUTXF0 I/OFX0
0
xx
62H
Bits
0
1
2
3
4
5
6
7
8-31
Status
0
1
0
Read-only
0
1
1
0
0
Signal Name
Reserved
I/OXFO
OUTXFO
INXFO
Reserved
I/OXF1
OUTXF1
INXFO
Reserved
Setting
Unused
XFO is an output pin
RESET (place a 0 on) XFO
Unused
Unused
Unused
Unused
Unused
Unused
Place the AIC in reset by bringing XFO pin low. This is done by
writing an 02 to the CPU’s IOF register.
Contents of ATABLE = 809c03
LDI
@ATABLE,AR1
;AR1=AIC init data
AR1  809c03
162c
809c04
0001
809c05
4892
809c06
67
The AIC must stay in a reset condition for at least 2 TCLK0
cycles.
RPTS
NOP
99
;repeat next instr 100 times
;keep IOF low for a while
LDI
131h,R0
;X & R port control register data
STI
R0,*+AR0(42h)
;FSX/DX/CLKX=SP operational pins
STI
R0,*+AR0(43h)
;FSR/DR/CLKR=SP operational pins
LDI
@SETSP,R0
;RESET->SP:16 bits,ext clks,std mode
STI
R0,*+AR0(40h)
;FSX=output & INT enable SP global reg
LDI
0,R0
;R0=0
STI
R0,*+AR0(48h)
;clear serial port XMIT register
OR
06h,IOF
;bring AIC out of reset
AR0 
LDI
STI
STI
131h,R0
R0,*+AR0(42h)
R0,*+AR0(43h)
;X & R port control register data
;FSX/DX/CLKX=SP operational pins
;FSR/DR/CLKR=SP operational pins
131
Bits
Status
Signal Name
Setting
1
CLKXFUNC
Serial port CLK
0
0
CLKXI/O
CLK is a general purpose input
1
0
CLKXDATAOUT Unused
2
Read-only CLKXDATAIN Unused
3
1
DXFUNC
Serial port data
4
1
DXI/O
DX is a general purpose output
5
0
DXDATAOUT Unused
6
Read-only
DXDATAIN
Unused
7
1
FSXFUNC
Serial port frame sync
8
0
FSXI/O
FSX is a general purpose input
9
0
FSXDATAOUT Unused
10
FSXDATAIN
Unused
11 Read-only
0
Reserved
Unused
12-31
131
Bits
Status
Signal Name
Setting
1
CLKRFUNC
Unused
0
0
CLKRI/O
Unused
1
0
CLKRDATAOUT Unused
2
Read-only CLKRDATAIN Unused
3
1
DRFUNC
Unused
4
1
DRI/O
Unused
5
0
DRDATAOUT Unused
6
Read-only
DRDATAIN
Unused
7
1
FSRFUNC
Unused
8
0
FSRI/O
Unused
9
0
FSRDATAOUT Unused
10
FSRDATAIN
Unused
11 Read-only
0
Reserved
Unused
12-31
NOTE for this
problem that the
input A/D is not
used. Only the
D/A is used to
generate the sine
wave
AR0 
LDI
@SETSP,R0
;RESET->SP:16 bits,ext clks,std mode
STI
R0,*+AR0(40h)
;FSX=output & INT enable SP global reg
AR0 
LDI
STI
STI
131h,R0
R0,*+AR0(42h)
R0,*+AR0(43h)
;X & R port control register data
;FSX/DX/CLKX=SP operational pins
;FSR/DR/CLKR=SP operational pins
0E970300
Bits
0
1
2
3
4
5
6
7
8
9
10
11
Status
Read-only
Read-only
0
Read-only
Read-only
0
0
0
1
1
0
0
Signal Name
RRDY
XRDY
FSXOUT
XSREMPTY
RSRFULL
HS
XCLKSRCE
RCLKSRCE
XVAREN
RVAREN
XSFM
RSFM
Setting
Unused
Unused
External frame sync input
Unused
Unused
Handshake disabled
External transmit clock source
External receive clock source
Variable mode transmit
FSX is a general purpose input
Standard transmit frame mode
Standard receive frame mode
0E970300
Bits
12
13
14
15
16
17
18-19
20-21
22
23
Status
0
0
0
0
1
1
01
01
0
1
Signal Name
CLKXP
CLKRP
DXP
DRP
FSXP
FSRP
XLEN
RLEN
XTINT
XINT
Setting
Active-high CLKX
Active-high CLKR
Active-high transmit data
Active-high receive data
Active-low FSX
Active-low FSR
16-bit word transmission
16-bit word reception
Transmit timer interrupt disabled
Transmit interrupt enabled
0E970300
Bits
24
25
26
27
28-31
Status
0
1
1
1
0
Signal Name
RTINT
RINT
XRESET
RRESET
FSXP
Setting
Receive timer interrupt disabled
Receive interrupt enabled
Reset transmit
Reset receive
Unused
The FSX and FSR frame syncs act as active-low inputs from the
AIC. The DX and DR data signals remain active high. Both
transmitted and received words are 16 bits in length. This
configuration sets the serial port mode for a standard mode (i.e.
not continuous mode) with a variable data rate. A variable data
rate mode works with AIC’s timing protocol, whereas a fixed
data rate mode does not.
AR0 
The XMIT (transmit) register is
cleared by writing 0s into each
bit.
LDI
0,R0
;R0=0
STI
R0,*+AR0(48h)
;clear serial port XMIT register
AR0 
LDI
LDI
RPTS
NOP
62h,IOF
@ATABLE,AR1
99
LDI
OR
62h,IOF
06h,IOF
IOF (IO Flag Register)
31-16
15-12
11-8
xx
xx
xx
7
;AIC reset = 0
;AR1=AIC init data
;repeat next instr 100 times
;keep IOF low for a while
;AIC reset = 0
;bring AIC out of reset
A logical 0 resets the AIC; a
logical 1 brings the AIC out
of reset.
6
5
INXF1 OUTXF1 I/OFX1
4
xx
3
2
1
INXF0 OUTXF0 I/OFX0
0
xx
RPTS
NOP
99
;repeat next instr 100 times
;keep IOF low for a while
The RESET line brought low and remains for 100 NOPs.
Contents of ATABLE = 809c03
LDI
@ATABLE,AR1
;AR1=AIC init data
This instruction establishes AR1 as a pointer to the table
containing the information that sets the sampling frequency
and the bandwidth of the antialiasing and reconstruction filters,
as well as other constants used by the DSP.
AR1  809c03
162c
809c04
0001
809c05
4892
809c06
67
Four values are defined in ATABLE. The first and third values
define the sampling rate.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
1
0
1
1
X
X
0
1
0
1
1
0
0
0
1
0
162c
RA
TA
X
1
0
0
TB
1
0
0
X
4892
1
0
0
1
0
RB
MCLK
6.25 MHz
Fs 

 8 kHz
2 * TA * TB 2 *11* 36
The second value in table ATABLE sets TA’ and RA’ to zero
implying that the sampling frequency will be determined only by
TA and TB.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
0
0
0
0
X
X
0
0
0
0
0
0
1
T’A
R’A
The fourth value of the table is the contents of the control
register.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
0
1
1
0
0
1
1
1
Inserts antialiasing
filter
The signal varies
between  3 volts.
Synchronous transmit
receive sections
Disables auxiliary
input.
Disables loopback function.