Transcript Document 7809950

Verilog Basics
Nattha Jindapetch
November 2008
Agenda
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Logic design review
Verilog HDL basics
LABs
Logic Design Review
Basic Logic gates
Additional Logic Gates
Two Types
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Combinational circuit
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No "memory"
Its output depends only upon the current
state of its inputs.
Sequential circuit
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Contains memory elements
Its output depends not only upon the current
state of its inputs, but also on the current
state of the circuit itself.
Two Styles: Synchronous and Asynchronous
Combinational Circuits: examples
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Multiplexers
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2n x 1 multiplexer receives 2n input bits and n selector
bits, and outputs exactly one of the input bits,
determined by the pattern of the selector bits.
Combinational Circuits: examples
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Demultiplexers
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1 x 2n DMUX is the
inverse of MUX
It takes 1 input and
transmits that input on
exactly one of its outputs,
determined by the
pattern of its n selector
bits.
Combinational Circuits: examples
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Encoders
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2n x n encoder takes 2n
inputs and sets each of
its n outputs, based
upon the pattern of its
inputs.
an encoder is the
inverse of a decoder.
Combinational Circuits: examples
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Decoders
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An n x 2n decoder
takes n inputs and
sets exactly one of
its 2n outputs,
based upon the
pattern of its
inputs.
Sequential Circuits
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R
Circuits with feedback
Q
Q'
S
R
0
1
0
1
Cross-coupled NOR gates
S
0
0
1
1
Q Q’
No change
0 1 Reset
1 0 Set
Not allowed
Sequential Elements
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Latches vs Flip-Flops
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Latches work on Level-sensitive
Flip-Flops work on Edge-triggered
RS, JK, D, T
S
R
Q Q’
J
K
Q Q’
0
0
No change
D
Q
T
Q
0
0
No change
0
1
0
1 Reset
0
0
0
1
0
1
0
1
1
1
1
0
1
0
1
0 Set
1
0
1
0
1
1
1
1
Toggle
Not allowed
Counters
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Synchronous counter
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Clock of synchronous
counter are same clock.
Asynchronous counter
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Clock of second flipflop is Q of first flipflop.
The clock of
asynchronous counter
are different source.
Registers
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A register is used for storing several bits of
digital data.
It basically consists of a set of flip-flops.
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each flip-flop representing one bit of the register.
Thus, an n-bit register has n flip-flops.
A Simple Shift Register Consisting of D-type Flip-flops
Verilog HDL basics
HDL (Hardware Description Language)
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Big picture: Two main HDLs out there
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VHDL
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Verilog HDL
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Designed by committee on request of the
Department of Defense
Based on Ada
Designed by a company for their own use
Based on C
Both now have IEEE standards
Both are in wide use
Verilog Description Styles
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Verilog supports a variety of description
styles
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Structural
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Behavioral
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explicit structure of the circuit
e.g., each logic gate instantiated and connected to
others
program describes input/output behavior of
circuits
Mixed
Verilog Module
module module-name (list-of-port);
input/output declarations
local net declarations
parallel statements
endmodule
Structural Module: example1
module half_adder (s, a, b, co);
input
a, b;
output
s, co;
wire
w0, w1, w2;
assign
w0 = a & b,
w1 = ~w0,
w2 = a | b,
s = w1 & w2,
co = w0;
endmodule
co
a
b
w0
w1
s
w2
a
b
s
co
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
Structural Module: example1
module full_adder (s, a, b, co, ci);
input
a, b, ci;
output
s, co;
a
i0
a
co
w1
co
HA
b
wire
w0, w1, w2;
w0
assign
co = w1 | w2;
half_adder i0
(.co(w1), .s(w0), .a(a), .b(b)); ci
half_adder i1
(.co(w2), .s(s), .a(w0), .b(ci));
endmodule
b
s
i1
a
co
HA
b
s
w2
s
Structural Module: example1
module adder4
input [3:0]
input ci;
output [3:0]
output
(s, a, b, co, ci);
a, b;
s,
co;
wire
w0, w1, w2;
full_adder i0
(.co(w0), .s(s[0]), .a(a[0]), .b(b[0]),
.ci(ci));
full_adder i1
(.co(w1), .s(s[1]), .a(a[1]), .b(b[1]),
.ci(w0));
full_adder i2
(.co(w2), .s(s[2]), .a(a[2]), .b(b[2]),
.ci(w1));
full_adder i3
(.co(co), .s(s[3]), .a(a[3]), .b(b[3]),
.ci(w2));
endmodule
ci
a[0]
b[0]
i0
ci
a
b
a[1]
b[1]
i1
ci
a
b
a[2]
b[2]
i2
ci
a
b
a[3]
b[3]
i3
ci
a
b
FA
s
co
FA
s
co
FA
s
co
FA
s
co
s[0]
w0
s[1]
w1
s[2]
w2
s[3]
co
Behavioral Module: example1
module adder4 (s, a, b, co, ci);
input
[3:0] a, b;
input
ci;
output [3:0]
s,
output
co;
reg [3:0] s;
reg co;
always @(a or b or ci)
{co, s} = a + b + ci;
endmodule
Verilog Data Types
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Possible Values:
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0: logic 0, false
1: logic 1, true
X: unknown logic value
Z: High impedance state
Registers and Nets (wires) are the main data
types
Integer, time, and real are used in behavioral
modeling, and in simulation
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Note that they are not synthesized !
Verilog Registers
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Abstract model of a data storage element
A reg holds its value from one assignment
to the next
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The value “sticks”
Register type declarations
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reg a; // a scalar register
reg [3:0] b; // a 4-bit vector register
Verilog Nets
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Nets (wires) model physical connections
They don’t hold their value
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They must be driven by a “driver” (i.e. a
gate output or a continuous assignment)
Their value is Z if not driven
Wire declarations
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wire d; // a scalar wire
wire [3:0] e; // a 4-bit vector wire
Verilog Parameters
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Used to define constants
parameter size = 16, value = 8;
wire [size-1:0] bus; // defines a 15:0 bus
Verilog Operators
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Arithmetic operators:
Logical operators:
Bitwise operators:
Equality operators:
Relational operators:
Reduction operators:
Shift operators:
Conditional:
+, -, *, /, %
&&, ||, !
&, |, ~, ^, ^~
==, !=,
>, <, >=, <=
&, ~&, |, ~|, ^
>>, <<
?:
Example2: 4:1 multiplexer
module mux4 (s, d, z); //bitwise operators
input [1:0] s;
input [3:0] d;
output z;
assign z =(~s[1] & ~s[0] & d[0]) |
(~s[1] & s[0] & d[1]) |
( s[1] & ~s[0] & d[2]) |
( s[1] & s[0] & d[3]) ;
endmodule
Example2: 4:1 multiplexer
module mux4 (s, d, z); //using conditional operators
input [1:0] s;
input [3:0] d;
output z;
assign z = s[1] ? (s[0] ? d[3] : d[2]) : (s[0] ? d[1] : d[0]);
endmodule
Verilog Assignments
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Two types:
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Continuous Assignments
 assign values to nets
 This means combinational logic
Procedural Assignments
 assign values to registers
 Only allowed inside procedural blocks
(initial and always)
Continuous Assignments
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Models combinational logic using a logical
expression instead of gates
Assignment is evaluated whenever any signal
changes
wire a, b, out;
assign out = ~(a & b);
wire [15:0] sum, a, b;
wire cin, cout;
assign {cout,sum} = a + b + cin;
Procedural Assignments
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Assigns values to register types
They do not have a duration
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They occur only within procedural
blocks
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The register holds the value until the next
procedural assignment to that variable
initial and always
They are triggered when the flow of
execution reaches them
always Blocks
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When is an always block executed?
 always
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always @(a or b or c)
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Whenever there is a change on a, b, or c
Used to describe combinational logic
always @(posedge foo)
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Starts at time 0
Whenever foo goes from low to high
Used to describe sequential logic
always @(negedge bar)
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Whenever bar goes from high to low
Inside always blocks
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Procedural assignments
if statements
case statements
for, while, forever statements
wait statements
Blocking vs Non-blocking
Blocking vs Non-blocking
Blocking
begin
end
q1 = x1;
q2 = q1;
z1 = q2;
Non-Blocking
begin
end
q1 <= x1;
q2 <= q1;
z1 <= q2;
Quick Review
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Continuous assignments to wires
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assign variable = exp;
Result in combinational logic
Procedural assignment to regs
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Always inside procedural blocks (always blocks in
particular for synthesis)
blocking
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non-blocking
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variable = exp;
variable <= exp;
Can result in combinational or sequential logic
Quick Review
module name (args…);
input …; // define inputs
output …; // define outputs
wire… ;
reg …;
// internal wires
// internal regs, possibly output
// the parts of the module body are
// executed concurrently
<continuous assignments>
<always blocks>
endmodule
comment in Verilog_HDL
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// Single-line comment
/*………….
…………..*/ multiple-line comment
module mux2_1(out,a,b,sel); // port declare.
input a,b,sel;
output out;
wire sel_,a1,b1
/* structural design using logic operator
mux2_1 */
not (sel_,sel);
and (a1,a,sel),(b1,b,sel);
or (out,a1,b1);
endmodule;
Naming in Verilog_HDL
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ื่ ไฟล์ กำรตัง้ ชอ
ื่ อุปกรณ์ และ
ข ้อกำหนด ในกำรตัง้ ชอ
ื่ มต่อ
กำรเชอ
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ั ญำณ จะต ้องไม่เป็ นคำสงวนของภำษำ
สำยสญ
ระหว่ำงข ้อควำม หรือตัวเลข สำมำรถใช ้ เครือ
่ งหมำย _
หรือ $ ได ้
ื่ ต ้องเป็ น ตัวอักษร a-z หรือ A-Z หรือ _
ตัวแรกทีต
่ งั ้ ชอ
ตัวอักษรตัวใหญ่ และ ตัวเล็ก จะมีควำมหมำยแตกต่ำงกัน
ึ ษาเพิม
ศก
่ เติม ....
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