Transcript Interface Design Compute Memory Timing Omid Fatemi

Interface Design
Compute
Memory Timing
Omid Fatemi
([email protected])
University of Tehran 1
Outline
• Connecting to micro-processor
• Timing of microprocessor
• Timing of memory
• Interfacing memory
University of Tehran 2
Typical Interface Design
Connect
Sense Reality
Touch Reality
Connect
Transform
Compute
Embedded Systems
Micros
Assembler, C
Real-Time
Memory
Peripherals
Timers
DMA
Convey
PC interfaces
HCI
Cooperate
Busses
Protocols
Standards
PCI
IEEE488
SCSI
USB & FireWire
CAN
University of Tehran 3
Processor Timing Diagram
for any memory read machine cycle
T1
T2
T3
CLOCK
___
IOR
____
IOW
_____
MEMR
______
MEMW
Address
Bus
Data Bus
memory address
data
in
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Processor Timing Diagram
for any memory write machine cycle
T1
T2
T3
CLOCK
___
IOR
____
IOW
_____
MEMR
______
MEMW
Address
Bus
Data Bus
memory address
data out
University of Tehran 5
When interfacing memory chips to a
microprocessor, consider the following:
•
•
•
•
•
TAVDV – address access time
TRLDV – read access time
TDVWH – memory setup time
TWHDX – data hold time
TWLWH – write pulse width
Refer to 8088 data manual
University of Tehran 6
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
D7 - D0 (from memory)
from m e m ory to 74LS245
AD7 - AD0
A7 - A0
garbage
A15 - A8
A19/S6 - A16/S3
D7 - D0 from
74LS245
A15 - A8
A19 - A16
S6 - S3
A19 - A0
A19 - A0 from 74LS373
from 74LS373 to m e m ory
__
IO/M
____
RD
______
DEN
TAVDV
3TCLCL
Address Access Time
(TAVDV)
TDVCL
TCLAV
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Timing Requirements during
Memory Read
• TAVDV
– 3TCLCL – TCLAV – TDVCL
– Address Access Time
– from Address is Valid to Data is Valid
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T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
D7 - D0 (from memory)
from m e m ory to 74LS245
AD7 - AD0
A7 - A0
garbage
A15 - A8
A19/S6 - A16/S3
D7 - D0 from
74LS245
A15 - A8
A19 - A16
S6 - S3
A19 - A0
A19 - A0 from 74LS373
from 74LS373 to m e m ory
__
IO/M
____
RD
______
DEN
TRLDV
2TCLCL
Read Access Time
(TRLDV)
TCLRL
TDVCL
University of Tehran 9
Timing Requirements during
Memory Read
• TRLDV
– 2TCLCL – TCLRL – TDVCL
– Read Access Time
– from Read Signal is Low to Data is Valid
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T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
D7 - D0 (to memory)
A7 - A0
D7 - D0 (to 74LS245)
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to m e m ory
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TDVWH
2TCLCL
Memory Setup Time
(TDVWH)
TCLDV
TCVCTX
University of Tehran 11
Timing Requirements during
Memory Write
• TDVWH
– 2TCLCL – TCLDV +TCVCTX
– Memory Setup Time
– from Data is Valid to Write Signal is High
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T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
A7 - A0
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to m e m ory
D7 - D0 (to memory)
D7 - D0 (to 74LS245)
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TWHDX
TCLCH
Data Hold Time (TWHDX)
University of Tehran 13
Timing Requirements during
Memory Write
• TWHDX
– TCLCH – X
– Data Hold Time (after WR’)
– from Write Signal is High to Data is Invalid (Inactive)
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T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
A7 - A0
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to m e m ory
D7 - D0 (to memory)
D7 - D0 (to 74LS245)
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TWLWH
2TCLCL
Write Pulse Width / WriteTime (TWLWH)
University of Tehran 15
Timing Requirements during
Memory Write
• TWLWH
– 2TCLCL – Y
– Write Pulse Width / Write-Time
– from Write Signal is Low to Write Signal is High
University of Tehran 16
8088 MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
Symbol
Parameter
8088
Min
8088-2
Max
Min
Max
Units
TCLCL
CLK Cycle Period
200
TCLCH
CLK Low Time
118
68
ns
TDVCL
Data Setup Time
30
20
ns
TCLAV
Address Valid Delay
10
110
10
60
ns
TCLRL
RD’ Active Delay
10
165
10
100
ns
TCLDV
Data Valid Delay
10
110
10
60
ns
10
110
10
70
ns
TCVCTX Control Inactive Delay
TWHDX
Data Hold Time after WR’
TWLWH
WR’ Width
500
125
500
ns
TCLCH – 30
TCLCH – 30
ns
2TCLCL – 60
2TCLCL – 40
ns
University of Tehran 17
Computation of Timing Requirements for
8088 using a 4Mhz Clock
• TAVDV
 3TCLCL – TCLAVmax – TDVCLmin
 3(250 ns) – 110 ns – 30 ns
 610 ns
• TRLDV
 2TCLCL – TCLRLmax – TDVCLmin
 3(250 ns) – 165 ns – 30 ns
 555 ns
University of Tehran 18
8088 MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
Symbol
Parameter
8088
Min
8088-2
Max
Min
Max
Units
TCLCL
CLK Cycle Period
200
TCLCH
CLK Low Time
118
68
ns
TDVCL
Data Setup Time
30
20
ns
TCLAV
Address Valid Delay
10
110
10
60
ns
TCLRL
RD’ Active Delay
10
165
10
100
ns
TCLDV
Data Valid Delay
10
110
10
60
ns
10
110
10
70
ns
TCVCTX Control Inactive Delay
TWHDX
Data Hold Time after WR’
TWLWH
WR’ Width
500
125
500
ns
TCLCH – 30
TCLCH – 30
ns
2TCLCL – 60
2TCLCL – 40
ns
University of Tehran 19
Computation of Timing Requirements for
8088 using a 4Mhz Clock
• TDVWH
 2TCLCL – TCLDVmax +TCVCTXmin
 2(250 ns) – 110 ns + 10 ns
 400 ns
• TWHDX
 TCLCH – X
 118 ns – 30 ns
 88 ns
• TWLWH
 2TCLCL – Y
 2(250 ns) – 60 ns
 440 ns
University of Tehran 20
Timing Requirements for 8088 using a
4Mhz Clock
•
•
•
•
•
TAVDV = 610 ns
TRLDV = 555 ns
TDVWH = 400 ns
TWHDX = 88 ns
TWLWH = 440 ns
University of Tehran 21
Can we interface a 6264 to the 8088
chip which uses a 4MHz clock?
University of Tehran 22
Timing Requirements for 6264 SRAM
•
•
•
•
•
TAVDV = ?
TRLDV = ?
TDVWH = ?
TWHDX = ?
TWLWH = ?
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HM6264B Series Read TIMING
REQUIREMENTS
Symbol
Parameter
HM6264B-8L
Min
Max
HM6264B-10L
Min
Max
Units
tRC
Read cycle time
tAA
Address access time
85
100
ns
tCO1
Chip select access time (CS1’)
85
100
ns
tCO2
Chip select access time (CS2’)
85
100
ns
tOE
Output enable to output valid
45
50
ns
tLZ1
tLZ2
Chip selection to output in low -Z
(CS1)
Chip selection to output in low -Z
(CS2)
tOLZ
Output enable to output in low -Z
tHZ1
tHZ2
Chip deselection in to output i n
high-Z (CS1’)
Chip deselection in to output in
high-Z (CS2’)
tOHZ
tOH
85
100
ns
10
10
ns
10
10
ns
5
5
ns
0
30
0
35
ns
0
30
0
35
ns
Output disable to output in high -Z
0
30
0
35
ns
Output hold from address change
10
10
ns
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HM6264B Series Write TIMING
REQUIREMENTS
Symbol
Parameter
HM6264B-8L
Min
Max
HM6264B-10L
Min
Max
Units
tWC
Write cycle time
85
100
ns
tCW
Chip selection to end of write
75
80
ns
tAS
Address setup time
0
0
ns
tAW
Address valid to end of write
75
80
ns
tWP
Write pulse width
55
60
ns
tWR
Write recovery time
0
0
tWHZ
WE’ to output in high-Z
0
tDW
Data to write time overlap
40
40
ns
tDH
Data hold from write time
0
0
ns
tOW
Output active from end of write
5
5
ns
tOHZ
Output disable to output in high-Z
0
30
30
0
0
35
35
ns
ns
University of Tehran 25
HM6264B Series Read Timing
Diagram
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HM6264B Series Write Timing
Diagram
University of Tehran 27
Timing Requirements for 6264 SRAM
•
•
•
•
•
TAVDV = tAA
TRLDV = tOE
TDVWH = tDW
TWHDX = tDH
TWLWH = tWP
University of Tehran 28
Timing Requirements for HM6264B-8L
•
•
•
•
•
TAVDV = tAA = ?
TRLDV = tOE = ?
TDVWH = tDW = ?
TWHDX = tDH = ?
TWLWH = tWP = ?
University of Tehran 29
HM6264B Series Read TIMING
REQUIREMENTS
Symbol
Parameter
HM6264B-8L
Min
Max
HM6264B-10L
Min
Max
Units
tRC
Read cycle time
tAA
Address access time
85
100
ns
tCO1
Chip select access time (CS1’)
85
100
ns
tCO2
Chip select access time (CS2’)
85
100
ns
tOE
Output enable to output valid
45
50
ns
tLZ1
tLZ2
Chip selection to output in low-Z
(CS1)
Chip selection to output in low-Z
(CS2)
tOLZ
Output enable to output in low-Z
tHZ1
tHZ2
Chip deselection in to output in
high-Z (CS1’)
Chip deselection in to output in
high-Z (CS2’)
tOHZ
tOH
85
100
ns
10
10
ns
10
10
ns
5
5
ns
0
30
0
35
ns
0
30
0
35
ns
Output disable to output in high-Z
0
30
0
35
ns
Output hold from address change
10
10
ns
University of Tehran 30
HM6264B Series Write TIMING
REQUIREMENTS
Symbol
Parameter
HM6264B-8L
Min
Max
HM6264B-10L
Min
Max
Units
tWC
Write cycle time
85
100
ns
tCW
Chip selection to end of write
75
80
ns
tAS
Address setup time
0
0
ns
tAW
Address valid to end of write
75
80
ns
tWP
Write pulse width
55
60
ns
tWR
Write recovery time
0
0
tWHZ
WE’ to output in high-Z
0
tDW
Data to write time overlap
40
40
ns
tDH
Data hold from write time
0
0
ns
tOW
Output active from end of write
5
5
ns
tOHZ
Output disable to output in high-Z
0
30
30
0
0
35
35
ns
ns
University of Tehran 31
Timing Requirements for HM6264B-8L
•
•
•
•
•
TAVDV = tAA = 85 ns
TRLDV = tOE = 45 ns
TDVWH = tDW = 40 ns
TWHDX = tDH = 0 ns
TWLWH = tWP = 55 ns
University of Tehran 32
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and HM6264B-8L
8088 using 4MHz clk
610 ns
555 ns
400 ns
88 ns
440 ns
Timing Req.
TAVDV or tAA
TRLDV or tOE
TDVWH or tDW
TWHDX or tDH
TWLWH or tWP
HM6264B-8L
85 ns
45 ns
40 ns
0 ns
55 ns
University of Tehran 33
Can we interface a 2764 to the 8088
chip which uses a 4MHz clock?
University of Tehran 34
Timing Requirements for 2764 EPROM
•
•
•
•
•
TAVDV = ?
TRLDV = ?
TDVWH = ?
TWHDX = ?
TWLWH = ?
University of Tehran 35
M2764A Read Mode AC
Characteristics
Symbol
Alt
tAVQV
tACC
tELQV
tCE
tGLQV
tOE
tEHQZ
tDF
tGHQZ
tDF
tAXQX
tDH
Parameter
Address Valid to Output
Valid
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Ourput Hi-Z
Output Enable High to
Output Hi-Z
Address Transition to
Output Transition
-3
Min
-4
Max
Min
Max
Units
180
200
ns
180
200
ns
65
75
ns
0
55
0
55
ns
0
55
0
55
ns
0
0
ns
University of Tehran 36
M2764A Read Mode Timing
Diagram
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Timing Requirements for 2764 EPROM
•
•
•
•
•
TAVDV = tAVQV
TRLDV = tGLQV
TDVWH = N/A
TWHDX = N/A
TWLWH = N/A
University of Tehran 38
Timing Requirements for 2764 EPROM
•
•
•
•
•
TAVDV = tAVQV = ?
TRLDV = tGLQV = ?
TDVWH = N/A
TWHDX = N/A
TWLWH = N/A
University of Tehran 39
M2764A Read Mode AC
Characteristics
Symbol
Alt
tAVQV
tACC
tELQV
tCE
tGLQV
tOE
tEHQZ
tDF
tGHQZ
tDF
tAXQX
tDH
Parameter
Address Valid to Output
Valid
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Ourput Hi-Z
Output Enable High to
Output Hi-Z
Address Transition to
Output Transition
-3
Min
-4
Max
Min
Max
Units
180
200
ns
180
200
ns
65
75
ns
0
55
0
55
ns
0
55
0
55
ns
0
0
ns
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Timing Requirements for M2764A-3
•
•
•
•
•
TAVDV = tAVQV = 180 ns
TRLDV = tGLQV = 65 ns
TDVWH = N/A
TWHDX = N/A
TWLWH = N/A
University of Tehran 41
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and M2764A-3
8088 using 4MHz clk
610 ns
555 ns
Timing Req.
TAVDV or tAVQV
TRLDV or tGLQV
HM6264B-8L
180 ns
65 ns
University of Tehran 42
What if we need to interface a
“slow” memory to the 8088?
University of Tehran 43
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and a certain “slow” memory chip
8088 using 4MHz clk
610 ns
555 ns
400 ns
88 ns
440 ns
Timing Req.
TAVDV or tAA
TRLDV or tOE
TDVWH or tDW
TWHDX or tDH
TWLWH or tWP
memory chip
85 ns
45 ns
40 ns
0 ns
500 ns
University of Tehran 44
A12
:
A19
A18
A17
A16
A15
A14
A13
READY
A0
Q7
:
M2764A-3
Q0
G
C
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
SLOW
MEMORY
CS
A12
:
A0
D7
:
HM6264B-8L
D0
OE
WE
CS1
CS2
5V
University of Tehran 45
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
A7 - A0
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to m e m ory
D7 - D0 (to memory)
D7 - D0 (to 74LS245)
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TWLWH
2TCLCL
Recall:Write Pulse Width /
Write-Time (TWLWH)
University of Tehran 46
T1
T2
TW
T3
T4
CLOCK
READY
__
DT/R
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
D7 - D0 (to memory)
A7 - A0
D7 - D0 (to 74LS245)
A15 - A8
A15 - A8
A19/S6 - A16/S3
A19 - A16
A19 - A0
from 74LS373 to m e m ory
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
TWLWH
Write Pulse Width / Write-Time (TWLWH)
w/ 1 wait state
University of Tehran 47
Comparing Timing Requirements of
8088 (using 4 Mhz clock) and a certain memory chip
8088 using 4MHz clk
610 ns
555 ns
400 ns + 250 ns
88 ns + 250 ns
440 ns + 250 ns
Timing Req.
TAVDV or tAA
TRLDV or tOE
TDVWH or tDW
TWHDX or tDH
TWLWH or tWP
memory chip
85 ns
45 ns
40 ns
0 ns
500 ns
caused by 1 wait state during a memory
write on the “slow” memory chip
University of Tehran 48
How do we produce a wait
state?
• By turning the READY input of the 8088
microprocessor to LOW
University of Tehran 49
A12
:
A19
A18
A17
A16
A15
A14
A13
READY
A0
Q7
:
M2764A-3
Q0
G
C
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
SLOW
MEMORY
CS
A12
:
A0
D7
:
HM6264B-8L
D0
OE
WE
CS1
CS2
5V
University of Tehran 50
T1
T2
TW
T3
T4
CLOCK
READY
__
DT/R
as much as possible
this should be LOW
before the end of T2 (if
it is not possible, it can
be late by at most 8ns)
ALE
D7 - D0
from 74LS245 to m e m ory
AD7 - AD0
A7 - A0
D7 - D0 (to memory)
A7 - A0
D7 - D0 (to 74LS245)
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to m e m ory
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
_____
WR
______
DEN
30 ns
(min)
119 ns
(min)
Requirements for the READY input of the 8088
University of Tehran 51
T1
T2
TW
T3
T4
CLOCK
RDY1
READY
35 ns
(min)
Requirements for the RDY of the 8284
University of Tehran 52
A12
:
A19
A18
A17
A16
A15
A14
A13
READY
A0
Q7
:
M2764A-3
Q0
G
C
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
SLOW
MEMORY
CS
A12
:
A0
D7
:
HM6264B-8L
D0
OE
WE
CS1
CS2
5V
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University of Tehran 54