Transcript Processor: Datapath and Control Chapter 5 1

Processor: Datapath and
Control
Chapter 5
1
Components of a Computer
Processor
Control
Datapath
Devices
Memory
Input
Output
2
Code Stored in Memory
Memory
Processor
Control
Datapath
000000
000000
100011
100011
101011
101011
000000
00000
00100
00010
00010
00010
00010
11111
00101
00010
01111
10000
10000
01111
00000
0001000010000000
0001000000100000
0000000000000000
0000000000000100
0000000000000000
0000000000000100
0000000000001000
Devices
Input
Output
3
Processor Fetches an Instruction
Processor fetches an instruction from memory
Memory
Processor
Control
Datapath
000000
000000
100011
100011
101011
101011
000000
00000
00100
00010
00010
00010
00010
11111
00101
00010
01111
10000
10000
01111
00000
0001000010000000
0001000000100000
0000000000000000
0000000000000100
0000000000000000
0000000000000100
0000000000001000
Devices
Input
Output
4
Control Decodes the Instruction
Control decodes the instruction to determine
what to execute
Processor
Devices
Control
000000 00100 00010 0001000000100000
Memory
Input
Datapath
Output
5
Datapath Executes the Instruction
Datapath executes the instruction as directed
by control
Processor
Devices
Control
000000 00100 00010 0001000000100000
Memory
Input
Datapath
contents Reg #4 ADD contents Reg #2
results put in Reg #2
Output
6
What Happens Next?
Memory
Processor
Control
Datapath
000000
000000
100011
100011
101011
101011
000000
00000
00100
00010
00010
00010
00010
11111
00101
00010
01111
10000
10000
01111
00000
0001000010000000
0001000000100000
0000000000000000
0000000000000100
0000000000000000
0000000000000100
0000000000001000
Devices
Input
Output
Fetch
Exec
Decode
7
Output Data Stored in Memory
At program completion the data to be output
resides in memory
Processor
Memory
Control
Datapath
Devices
Input
00000100010100000000000000000000
00000000010011110000000000000100
00000011111000000000000000001000
Output
8
Processor
• Two main components
– Datapath
– Control
9
Design of Processor
1. Analyze the instruction set architecture
2. Select the datapath elements each
instruction needs
3. Assemble the datapath
4. determine the controls required
5. Assemble the control logic
10
A Basic MIPS Implementation
• will implement the following subset of MIPS
core instructions
– lw, sw
– add, sub, and, or, slt
– beq, j
11
Steps in executing add instruction
add $t0, $t1, $t2
•
•
•
•
•
Send PC to memory that contains the
code and fetch instruction
PC = PC+4
Read $t1 and $t2 from register file
Perform $t1 + $t2
Store result in $t0
12
Steps in executing lw instruction
lw $t0, offset($t1)
•
•
•
•
•
•
Send PC to memory that contains the code
and fetch instruction
PC = PC+4
Read $t1 from register file
Perform $t1 + sign-extend(offset)
Read value at Mem[$t1 + sign-extend(offset)]
Store result in $t0
13
Steps in executing beq instruction
beq $t0, $t1, Label
•
•
•
•
•
Send PC to memory that contains the
code and fetch instruction
PC = PC+4
Read $t0 and $t1 from register file
Perform $t0 - $t1
If result = 0, set PC=Label
14
Steps in implementing these
instructions
• Common steps
– Send PC to memory that contains the code and fetch the
instruction
– Set PC = PC+4
– Read one or two registers
• Steps dependent on instruction class
– Use ALU
• Arithmetic/logical instr for operation execution
• lw/sw for address calculation
• beq for comparison
– Update memory or registers
• lw/sw read or write to memory
• Arithmetic/logical instr write to register
• beq updates PC
15
Components needed for Fetching
and Incrementing PC
Instruction
address
Instruction
PC
Add Sum
Instruction
memory
a. Instruction memory
b. Program counter
c. Adder
16
Datapath for Fetching and
Incrementing PC
17
Components needed for R-format
Instructions
add $t0, $t1, $t2: $t0= $t1 + $t2
and $t0, $t1, $t2: $t0= $t1 AND $t2
5
Register
numbers
5
5
Data
Read
register 1
4
Read
data 1
Read
register 2
Write
register
ALU operation
Zero
Data
Registers
ALU ALU
result
Read
data 2
Write
Data
RegWrite
a. Registers
b. ALU
18
Register File
• Consists of a set of 32
registers that can be read
and written
– Registers built from D flip-flops
• has two read ports and one
write port
• Register number are 5 bit
long
• To write, you need three
inputs:
– a register number, the data to
write, and a clock (not shown
explicitly) that controls the
writing into the register
– The register content will
change on rising clock edge
5
5
5
19
Portion of datapath for R-format
instruction
4
rs
rt
rd
R-format
31-26
25-21
20-16
15-11
10-6
5-0
opcode
rs
rt
rd
shamt
funct
20
Components needed for load and
store instructions
lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]
sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0
21
Memory Unit
MemRead
• MemRead to be
asserted to read
• MemWrite to be
asserted to write
• Both MemRead and
MemWrite not to be
asserted in same
clock cycle
• Memory is edge
triggered for writes
Address
ReadData
Write Data
MemWrite
22
Load/Store instruction datapath
lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]
sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0
4
I-format
31-26
25-21 20-16 15-0
opcode rs
rt
offset
23
Load instruction datapath
lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]
4
rs
rt
offset
I-format
31-26
25-21 20-16 15-0
opcode rs
rt
offset
24
Store instruction datapath
sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0
4
rs
rt
offset
I-format
31-26
25-21 20-16 15-0
opcode rs
rt
offset
25
Branch Instruction Datapath
rs
rt
C
31-26
25-21
20-16
15-0
opcode
rs
rt
C
If ($rs-$rt)=0, PC=PC+4+(C.4)
26
Creating a single Datapath
Simplest Design: Single Cycle Implementation
• Any instruction takes one clock cycle to execute
– This means no datapath elements can be used more
than once per instruction
– But datapath elements can be shared by different
instruction flows
27
4
4
28
Composite Datapath for R-format
and load/store instructions
29
Composite Datapath for R-format
and load/store instructions
4
+
P
C
Instruction
Memory
30
Composite datapath for R-format,
load/store, and branch instructions
31
Datapath for for R-format,
load/store, and branch instructions
ALU
Operation
4
32
Instruction
RegDst
RegWrite
ALUSrc
MemRead
MemWrite
MemToReg
PCSrc
ALU
operation
R-format
1
1
0
0
0
0
0
0000(and)
0001(or)
0010(add)
0110(sub)
lw
0
1
1
1
0
1
0
0010 (add)
sw
X
0
1
0
1
X
0
0010 (add)
beq
x
0
0
0
0
X
1 or 0
0110 (sub)
33
Control
• We next add the control unit that
generates
– write signal for each state element
– control signals for each multiplexer
– ALU control signal
• Input to control unit: instruction opcode
and function code
34
Control Unit
• Divided into two parts
– Main Control Unit
• Input: 6-bit opcode
• Output: all control signals for Muxes, RegWrite,
MemRead, MemWrite and a 2-bit ALUOp signal
– ALU Control Unit
• Input: 2-bit ALUOp signal generated from Main
Control Unit and 6-bit instruction function code
• Output: 4-bit ALU control signal
35
36
Truth Table for Main Control Unit
37
Main Control Unit
38
ALU Control Unit
• Must describe hardware to compute 4-bit ALU control
input given
– 2-bit ALUOp signal from Main Control Unit
– function code for arithmetic
• Describe it using a truth table (can turn into gates):
39
ALU Control bits
0010
0010
0110
0010
0110
0000
0001
0111
40
ALU Control Unit
41