Transcript ECE 5465 Advanced Microcomputers Chapter 1: Processor Architecture and Organization Hardware Design Abstraction MU0 1/20/2015 Processor Architecture  Computer Architecture describes the user’s view of the computer.     Instruction Set Visible Registers Memory.

ECE 5465
Advanced Microcomputers
Chapter 1:
Processor Architecture and Organization
Hardware Design Abstraction
MU0
1/20/2015
1
Processor Architecture
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Computer Architecture describes the user’s
view of the computer.
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Instruction Set
Visible Registers
Memory Management table structures
Exception handling
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Processor Organization
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Computer organization describes the userinvisible implementation of the architecture.
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Pipeline Structure
Transparent Cache
Table-walking Hardware
TLB
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What is a Processor?
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A finite state automaton that executes
instructions held in memory.
The state of the system is defined by the
values held in memory and the registers
within the processor
Lecture 1 - Introduction
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Stored Program Computer
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A computer that keeps its data and programs in the same
location.
 Allows for instructions to be treated as data
 Can write programs that change themselves
 (Typically bad practice, as it is hard to debug)
 Useful when overwriting old programs with new versions
 Is universal, as it can be programmed with an algorithm to
accomplish a task
Lecture 1 - Introduction
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Abstraction
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Computers are extremely complex and are simply a layout of a
LOT of transistors. How does this seemingly random array of
transistors accomplish anything?
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9/22/2010
A: Abstraction
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Abstraction Hierarchy
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A typical hierarchy of abstraction at the hardware level might be:
1. transistors;
2. logic gates, memory cells, special circuits;
3. single-bit adders, multiplexers, decoders, flip-flops;
4. word-wide adders, multiplexers, decoders, registers, buses;
5. ALUs (Arithmetic-Logic Units), barrel shifters, register banks,
memory blocks; 6. processor, cache and memory management
organizations;
7. processors, peripheral cells, cache memories, memory management
units;
8. integrated system chips;
9. printed circuit boards;
10. mobile telephones, PCs, engine controllers.
Lecture 1 - Introduction
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MU0 – A Simple Processor
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A simple processor can be built from a few components:
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Program counter (PC) that holds the address of the current
instruction
Accumulator (ACC) that holds data while it is worked upon
Arithmetic-logic Unit (ALU) that performs different operations
on binary operands
Instruction Register (IR) that holds the current instruction
while it’s executed
Instruction decode and control logic to achieve desired results
from instructions
Lecture 1 - Introduction
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The MU0 Instruction Set
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16-bit machine with 12-bit address space; can
address up to 8 Kbytes of memory
Instructions are 16 bits long; 4-bit opcode and
12-bit address field
Lecture 1 - Introduction
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MU0 Logic Design
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Two components:
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Datapath
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Comprised of components that carry, store, or process
many bits in parallel; these include the ACC, PC,
ALU, and IR. RTL design will be used for these
components.
Control Logic
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Everything that doesn’t fit into the datapath goes here;
a finite state machine (FSM) approach will be used.
Lecture 1 - Introduction
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Datapath Design
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Many ways to connect components of a
processor; memory is the limiting factor
in this design; it always takes a clock
cycle to perform a memory access
Each instruction takes exactly the
number of clock cycles defined by the
number of memory accesses it must
make
Need a datapath that has sufficient
resources to allow instructions to
complete in one or two clock cycles
Lecture 1 - Introduction
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Datapath Operation
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It is assumed that each instruction starts when
it has arrived in the IR
Potentially two stages for an instruction in
execution:
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Access memory operand and perform the desired
operation
Fetch the next instruction to be executed
Lecture 1 - Introduction
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Register Transfer Level (RTL) Design
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Registers change state on the
falling edge of the clock;
control signals can prevent
them from changing (PCce =
‘0’ stops the PC from changing)
Control logic decodes the
current instruction and
generates the appropriate levels
on datapath control signals
One-bit FSM comprised of
“fetch” and “execute” states
Lecture 1 - Introduction
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RTL Design Control Logic
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Table displays control logic
for MU0; can be
implemented as a
programmable logic array
(PLA) or translated into
combinatorial logic using
standard gates
‘x’ denotes “don’t care”
conditions
Some simplifications can be
made since some control
signals behavior similarly,
and they can be merged
Lecture 1 - Introduction
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ALU Design
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Five ALU functions:
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A+B: Normal adder output
A-B: Can be implemented as A+B+1, where B is inverted
B: A input and carry-in are set to 0
B+1: A input set to 0, carry-in set to 1
0 (Only used when reset is active)
Aen enables A operand or forces it to 0
Binv controls if B operand is inverted
Cout from one bit connected to Cin of the next
Lecture 1 - Introduction
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ALU logic for one bit
Lecture 1 - Introduction
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MU0 Extensions
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First ARM processors differented in complexity,
not principle
MU0 has spaces left in instruction space to allow
for future expansion of instruction set
Important potential extensions:
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Extend address space
Add more addressing modes
Allow PC to be saved (to support subroutines)
Add more registers and the support of interrupts
Lecture 1 - Introduction
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