Transcript Multicycle datapath - CMPE - EMU Department of Computer

Introduction: Review: Single Cycle and Multi-cycle
Datapath
How do we evaluate computer architectures?

Think of 5 characteristics that differentiate computers
—
—
—
—
—
—
—
—
Performance
Memory size
Instruction set
price
Reliability
Peripherals
Power consumption /heat dissipation
price
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Single-Cycle Performance
 In CMPE 325 we saw a MIPS single-cycle
datapath and control unit.
 In CMPE 421, we’ll explore factors that
contribute to a processor’s execution time,
and specifically at the performance of the
single-cycle machine.
 AND we’ll explore how to improve on the
single cycle machine’s performance using
pipelining.
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Three Components of CPU Performance
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Performance
3
Instructions Executed
 Instructions executed:
— not interested in the static instruction count, or how many lines of
code are in a program.
— Instead, the dynamic instruction count, or how many instructions are
actually executed when the program runs.
 There are three lines of code below, but the number of instructions
executed would be 2001.
BACK:
li
sub
bne
$a0, 1000
$a0, $a0, 1
$a0, $0, BACK
CPU timeX,P = Instructions executedP * CPIX,P * Clock cycle timeX
Cycles Per Instruction
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Performance
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CPI
 The average number of clock cycles per instruction, or CPI, is
a function of the machine and program.
— The CPI depends on the actual instructions appearing in
the program—a floating-point intensive application might
have a higher CPI than an integer-based program.
— It also depends on the CPU implementation. For example,
a Pentium can execute the same instructions as an older
80486, but faster.
 Remember In CMPE325, we assumed each instruction took
one cycle, so we had CPI = 1.
— The CPI can be >1 due to memory stalls and slow
instructions.
— The CPI can be <1 on machines that execute more than 1
instruction per cycle (superscalar, Duo Core, Quad core).
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Performance
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Clock cycle time
 One “cycle” is the minimum time it takes the CPU to do any
work.
— The clock cycle time or clock period is just the length of a
cycle.
— The clock rate, or frequency, is the reciprocal of the cycle
time.
 Generally, a higher frequency is better.
 Some examples illustrate some typical frequencies.
— A 500MHz processor has a cycle time of 2ns.
— A 2GHz (2000MHz) CPU has a cycle time of just 0.5ns
(500ps).
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Performance
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Execution time, again
CPU timeX,P = Instructions executedP * CPIX,P * Clock cycle timeX
 The easiest way to remember this is match up the units:
Seconds
Program
=
Instructions
*
Program
Clock cycles
Instructions
*
Seconds
Clock cycle
 Make things faster by making any component smaller!!
Program
Compiler
ISA
Organization
Technology
Instruction
Executed
CPI
Clock Cycle
TIme
 Often easy to reduce one component by increasing another
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Performance
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Example 1: ISA-compatible processors
 Let’s compare the performances two x86-based processors.
— An 800MHz AMD Duron, with a CPI of 1.2 for an MP3 compressor.
— A 1GHz Pentium III with a CPI of 1.5 for the same program.
 Compatible processors implement identical instruction sets and will use
the same executable files, with the same number of instructions.
 But they implement the ISA differently, which leads to different CPIs.
CPU timeAMD,P = InstructionsP * CPIAMD,P * Cycle timeAMD
=
= N x1.2x1/800=3/2000
CPU timeP3,P
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= InstructionsP * CPIP3,P * Cycle timeP3
=
= Nx1/5x1/1000=3/2000
Performance
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The single-cycle design from last time
0
M
u
x
Add
PC
4
Add
1
Shift
left 2
A control unit (not
shown) generates all
the control signals
from the instruction’s
“op” and “func” fields.
PCSrc
RegWrite
Read Instruction
address
[31-0]
MemWrite
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
0
I [15 - 11]
M
u
x
1
Read
register 2
Write
register
Write
data
Read
data 1
Zero
Read
data 2
Registers
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0
Result
M
u
x
1
ALUSrc
RegDst
I [15 - 0]
ALU
ALUOp
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
MemRead
Sign
extend
Multicycle datapath
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The example add from last time
 Consider the instruction add $s4, $t1, $t2.
000000
01001
01010
10100
00000
100000
op
rs
rt
rd
shamt
func
 Assume $t1 and $t2 initially contain 1 and 2 respectively.
 Executing this instruction involves several steps.
1. The instruction word is read from the instruction memory, and the
program counter is incremented by 4.
2. The sources $t1 and $t2 are read from the register file.
3. The values 1 and 2 are added by the ALU.
4. The result (3) is stored back into $s4 in the register file.
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Instruction execution review
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Example: Instruction Fetch (IF)
 Let’s quickly review how lw is executed in the single-cycle datapath.
 We’ll ignore PC incrementing and branching for now.
 In the Instruction Fetch (IF) step, we read the instruction memory.
RegWrite
Read Instruction
address
[31-0]
MemWrite
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
0
I [15 - 11]
M
u
x
1
Read
register 2
Write
register
Write
data
Read
data 1
Zero
Read
data 2
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0
Result
M
u
x
Registers
1
ALUSrc
RegDst
I [15 - 0]
ALU
ALUOp
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
MemRead
Sign
extend
Pipelining
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Instruction Decode (ID)
 The Instruction Decode (ID) step reads the source register from the
register file.
RegWrite
Read Instruction
address
[31-0]
MemWrite
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
0
I [15 - 11]
M
u
x
1
Read
register 2
Write
register
Write
data
Read
data 1
Zero
Read
data 2
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0
Result
M
u
x
Registers
1
ALUSrc
RegDst
I [15 - 0]
ALU
ALUOp
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
MemRead
Sign
extend
Pipelining
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Execute (EX)
 The third step, Execute (EX), computes the effective memory address
from the source register and the instruction’s constant field.
RegWrite
Read Instruction
address
[31-0]
MemWrite
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
0
I [15 - 11]
M
u
x
1
Read
register 2
Write
register
Write
data
Read
data 1
Zero
Read
data 2
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0
Result
M
u
x
Registers
1
ALUSrc
RegDst
I [15 - 0]
ALU
ALUOp
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
MemRead
Sign
extend
Pipelining
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Memory (MEM)
 The Memory (MEM) step involves reading the data memory, from the
address computed by the ALU.
RegWrite
Read Instruction
address
[31-0]
MemWrite
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
0
I [15 - 11]
M
u
x
1
Read
register 2
Write
register
Write
data
Read
data 1
Zero
Read
data 2
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0
Result
M
u
x
Registers
1
ALUSrc
RegDst
I [15 - 0]
ALU
ALUOp
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
MemRead
Sign
extend
Pipelining
17
Writeback (WB)
 Finally, in the Writeback (WB) step, the memory value is stored into the
destination register.
RegWrite
Read Instruction
address
[31-0]
MemWrite
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
0
I [15 - 11]
M
u
x
1
Read
register 2
Write
register
Write
data
Read
data 1
Zero
Read
data 2
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0
Result
M
u
x
Registers
1
ALUSrc
RegDst
I [15 - 0]
ALU
ALUOp
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
MemRead
Sign
extend
Pipelining
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How the add goes through the datapath
PC+4
0
M
u
x
Add
PC
4
Add
1
Shift
left 2
PCSrc=0
RegWrite=1
Read Instruction
address
[31-0]
I [25 - 21] 01001
I [20 - 16] 01010
Instruction
memory
0
I [15 - 11]
10100
M
u
x
1
RegDst
=1
I [15 - 0]
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MemWrite
Read
register 1
Read
register 2
Write
register
Write
data
Read
data 1
Read
data 2
Registers
MemToReg=0
00...01
ALU
00...10
Zero
0
Result
M
u
x
1
ALUSrc=0
Sign
extend
Multicycle datapath
ALUOp
=ADD
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
M
u
x
MemRead
00...11
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Performance of Single-cycle Design
CPU timeX,P = Instructions executedP * CPIX,P * Clock cycle timeX
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Performance
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Edge-triggered state elements
 In an instruction like add $t1, $t1, $t2, how do we know
$t1 is not updated until after its original value is read?
 We’ll assume that our state elements are positive edge
triggered, and are updated only on the positive edge of a
clock signal.
— The register file and data memory have explicit write
control signals, RegWrite and MemWrite. These units
can be written to only if the control signal is asserted
and there is a positive clock edge.
— In a single-cycle machine the PC is updated on each
clock cycle, so we don’t bother to give it an explicit
write control signal.
RegWrite
Read
register 1
Read
data 1
Read
register 2
Read
data 2
Write
register
Registers
Write
data
MemWrite
Read
address
Read
data
Write
address
Write
data
Data
memory
MemRead
PC
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The datapath and the clock
1. On a positive clock edge, the PC is updated with a new address.
2. A new instruction can then be loaded from memory. The control unit sets
the datapath signals appropriately so that
— registers are read,
— ALU output is generated,
— data memory is read or written, and
— branch target addresses are computed.
3. Several things happen on the next positive clock edge.
— The register file is updated for arithmetic or lw instructions.
— Data memory is written for a sw instruction.
— The PC is updated to point to the next instruction.

In a single-cycle datapath everything in Step 2 must complete within one
clock cycle, before the next positive clock edge.
How long is that clock cycle?
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Compute the longest path in the add instruction
PC+4
0
M
u
x
Add
PC
4
Add
2 ns
2 ns
RegWrite
Read Instruction
address
[31-0]
Read
register 1
I [20 - 16]
2 ns
0
I [15 - 11]
M
u
x
1
RegDst
I [15 - 0]
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PCSrc
0 ns
MemWrite
I [25 - 21]
Instruction
memory
1
Shift
left 2
0 ns
Read
data 1
Zero
Read
register 2
Read
data 2
Write
register
Write
data
ALU
Registers
0
Result
M
u
x
1
ALUOp
2 ns
1 ns
ALUSrc
Sign
extend
0 ns
Multicycle datapath
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
MemToReg
M
u
x
0 ns
MemRead
2 ns
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The slowest instruction...
 If all instructions must complete within one clock cycle, then the cycle
time has to be large enough to accommodate the slowest instruction.
 For example, lw $t0, –4($sp) is the slowest instruction needing __ns.
— Assuming the circuit latencies below.
Read Instruction
address
[31-0]
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
2 ns
0
I [15 - 11]
M
u
x
1
0 ns
I [15 - 0]
Read
data 1
Zero
Read
register 2
Read
data 2
Write
register
Write
data
ALU
0
M
u
x
Registers
1
0 ns
1 ns
Result
2 ns
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
M
u
x
0 ns
2 ns
Sign
extend
0 ns
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The slowest instruction...
 If all instructions must complete within one clock cycle, then the cycle
time has to be large enough to accommodate the slowest instruction.
 For example, lw $t0, –4($sp) needs 8ns, assuming the delays shown here.
reading the instruction memory
2n
s
reading the base register $sp
8ns
1n
Read Instruction
address
[31-0]
s
I [25computing
- 21]
memory
address $sp-4
Read
Read
register 1
I [20 - 16]
Instruction
memory
2 ns
data 1
ALU
s
Read
0
data 2
Writedata memory
M
reading
the
I [15 - 11]
Read
register 2
u
x
register
Write
data
Registers
s 1
0 ns
1 ns
storing
data
back
to
$t0
I [15 - 0]
Sign
Zero
0
M
u
x
1
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Result
2 ns2n
0 ns
Multicycle datapath
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
M
u
x
0 ns
2 ns
0 ns
extend
s
2n
1n
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...determines the clock cycle time
 If we make the cycle time 8ns then every instruction will take 8ns, even
if they don’t need that much time.
 For example, the instruction add $s4, $t1, $t2 really needs just 6ns.
reading the instruction memory
reading registers $t1 and $t2
computing $t1 + $t2
storing the result into $s0
Read Instruction
address
[31-0]
I [25 - 21]
Read
register 1
I [20 - 16]
Instruction
memory
2 ns
0
I [15 - 11]
M
u
x
1
0 ns
I [15 - 0]
Read
data 1
6 ns
ALU
Zero
Read
register 2
Read
data 2
Write
register
Write
data
2 ns
1 ns
2 ns
1 ns
0
M
u
x
Registers
1
0 ns
1 ns
Result
2 ns
Read
address
Read
data
1
Data
memory
0
Write
address
Write
data
M
u
x
0 ns
2 ns
Sign
extend
0 ns
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How bad is this?
 With these same component delays, a sw instruction would need 7ns, and
beq would need just 5ns.
 Let’s consider the gcc instruction mix from the textbook.
Instruction Frequency
Arithmetic
Loads
Stores
Branches
48%
22%
11%
19%
 With a single-cycle datapath, each instruction would require 8ns.
 But if we could execute instructions as fast as possible, the average time
per instruction for gcc would be:
(48% x 6ns) + (22% x 8ns) + (11% x 7ns) + (19% x 5ns) = 6.36ns
 The single-cycle datapath is about 1.26 times slower!
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Review of a Multiple Cycle Implementation



The root of the single cycle processor’s problems:
— The cycle time has to be long enough for the slowest instruction
Solution:
— Break the instruction into smaller steps
— Execute each step (instead of the entire instruction) in one cycle
• Cycle time: time it takes to execute the longest step
• Keep all the steps to have similar length
— This is the essence of the multiple cycle processor
The advantages of the multiple cycle processor:
— Cycle time is much shorter
— Different instructions take different number of cycles to complete
• Load takes five cycles
• Jump only takes three cycles
— Allows a functional unit to be used more than once per instruction
• Adder + ALU
• Instruction Memory + Data Memory
Summary
 Performance is one of the most important criteria in judging
systems.
— Here we’ll focus on Execution time.
 Our main performance equation explains how performance
depends on several factors related to both hardware and software.
CPU timeX,P = Instructions executedP * CPIX,P * Clock cycle
timeX
 It can be hard to measure these factors in real life, but this is a
useful guide for comparing systems and designs.
 A single-cycle CPU has two main disadvantages.
— The cycle time is limited by the worst case latency.
— It isn’t efficiently using its hardware.
 Next time, we’ll see how this can be rectified with pipelining.
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