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Computer Architecture: Intro
Anatomy of a CPU
J. Schmalzel
S. Mandayam
Objectives, 1
 Describe major functional elements of CISC, RISC
architectures
 Perform detailed analysis and synthesis of
combinatorial and sequential subsystems using
schematic and/or behavioral design capture w/ sim
 Describe principles and applications of the three
basic computing elements: CPU, MEM, I/O
 Use an embedded system that includes diverse
architectural features
Objectives, 2
 Apply analytic and simulation techniques to predict
and verify performance metrics
 Design an example architecture using SOTA tools
 Identify opportunities for hardware and software
trade-offs
 (Insert your objectives here…)
(
…and here)
Hierarchical View of EP and
Digital Systems
CPU
MEM
Computer
Architecture
I/O
Operating
System
HLLs
State
Machines
Interface
Method
MSI
Functions
Design
Techniques
Gates
Boolean
Algebra
Central Processing Unit (CPU)
 Controls
 Executes
 Computes (Fixed- and/or FloatingPoint)
Example EP Feature List
 Small footprint
 25.8 MHz CPU
 40 CMOS-compatible
parallel I/O lines
 Four CMOS-compatible
serial ports; max async rate of
806 kbps, max sync rate of 6.45
Mbps
 8-bit data bus
 13 address lines
 Control signals (I/O read,
write)
 Master/slave config
 Reset input, output
 5, 8-bit and 2, 10-bit
timers
 256K flash EPROM,
512KB SRAM
 RTC
 Status, WDT outputs
What’s Implied by Feature List?
 Tight confederation of functional elements
 Ability to control and sequence operations
 Well-defined interfaces to external memory
and I/O
A sample EP architecture looks like…
Block
Diagram
What about the CPU?
 The previous block diagram emphasized the
collection of I/O and control resources
 One step closer on the abstraction scale is to
look at the programmer’s model of the CPU
CPU Register Set (“Programmer’s Model”)
Internal CPU Architecture
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Program Counter
Address Unit
Instruction Register
Instruction Decoder
Register File
Control/Timing
Function Unit (ALU)
 Floating Point Unit
(FPU)
 Status Register
 Stack Register
 Index Register
Concept of CPU as Two Paths
 Data Path


Where data elements flow from/to
Where operations are performed
 Control Path

The source of data path control
Simple Model Data Path (7-18)
Dbus
W
n-bit bus
Register
Dadd
Signal
File
Aadd
Const
MBsel
MuxB
Aout
Dout
FS
Function
Status
MDsel
Unit
Din
MuxD
Dbus
Instruction Word
DA
AA
BA
MB
FS
MD RW
Instruction Set
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The way the EP computes and
performs operations
Load registers

Immediate

Memory

Indexed
Register-to-Register
Exchange Registers
Stack Operations
8- and 16-bit Arithmetic and
Logical Operations
Bit Set, Reset, Test
Increment/Decrement
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Shifts and Rotate
Block Moves
Program Flow Control
Fast A Instructions
Control
Privileged Instructions
Miscellaneous (e.g. NOP)
Questions, Comments, Discussion