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CONTENT
I.
Request
II.
CPU description
III.
Software for PID
IV.
System description
V.
Simulation Results
I. Request
 Design a simple processor (CPU)
 Use this CPU to design the PID controller by software.
 Design the circuits of the Plant and command in FPGA by hardware
 Simulate the overall close loop control system in Quartus II.
 Plot its response using Matlab.
I. Request
PID Control
Kp
E(n)
Ki z 1
1  z 1
u p n 
X_in
X(n)
+
E(n)
Y(n-1)
ui n 
K (1  z 1) u d n 
d
+
+
+
CPU
u n 
Yn (n)
Plant
plant
I. Request
Plant:
yn (n)   B1 y(n  1)  B2 y(n  2)  A0 x(n)  A1 x(n  1)  a2 x(n  2)
yn (n) /2 = 31048*y(n-1)-14828* y(n-2)+42*x(n)+ 80*x(n-1)+42*x(n-2)
 
 
PID control:
U z 1
K I z 1
1

K


K
(
1

z
)
p
d
1
1
Ez
1 z
Command error:
e(n) = x(n) – y(n)
U n  8 * K p * e(n)  ui (n  1)  K i * e(n  1)  K d * (e(n)  e(n  1))
I. Request
• Input values:
x(n) = 0.5 (or 16384 for Q15)
The first PID value: Kp = 5; Ki = 0.02; Kd = 0.8
The second PID value: Kp = 2; Ki = 0.1; Kd = 0.8
II. CPU Description
CPU Main Parts
+ Data Subsystem
Storage modules (registers)
Function modules (ALU)
Datapaths (switches, wires)
Control points (control signals are connected to the
modules)
Condition points (output signals used by control
subsystem)
+ Control Subsystem
Microinstruction format
Microprogram