Transcript ASPIC Front-end CCD Readout Circuit For LSST camera

ASPIC
Front-end CCD Readout Circuit
For LSST camera
LPNHE
C. Juramy, D. Martin, H. Lebbolo, P. Antilogus, P. Bailly, R. Sefri, S. Bailey
LAL
C. de La Taille, F. Wicek, J. Jeglot , M. Moniez, V. Tocut
Sefri Rachid @LPNHE
La Londe-les-Maures
october2009
1
IN2P3 contribution to camera
electronics
IN2P3 contribution:
Video Signal
Processing
CCD Clocks
3 serial
4 parallel
1 reset
Front End
Electronics
Clock / DSI
Timing /
Amplitude
SCC
16 outputs
500 X 2K
ASPIC
DSI
.
..
.
BackEnd
Electronics
analog
-100°C
18 bit
ADC’s
Back
End
Module
FPGA
(1/Raft)
digital
-40°C
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october2009
Scientific Data
21 Rafts
189 CCD’s
6GB / Frame
Timing
Control
Module
Warm
Electronics
2
ASPIC:
rst
1
proto
ASPIC: Analog Signal Processing IC
– 1rst prototype: mid 2007 to mid 2008
 2 solutions explored based on ‘Correlated Double
Sampling’
• With integrator : Dual Slope Integrator (DSI)
• Without integrator : ‘Clamp & Sample’
4 channels of each on the same silicium substrate to perform
crosstalk tests
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october2009
3
ASPIC:
Dual Slope Integrator
rst
1
proto
5K
100pF
5K
-
5K
outp
"diff DSI" outp
inp
+
10K
+
-
Vref
Vout
CCD output stage
CDS
8k 2p
8p
Vref
(switches)
2k
10K
100pF
Vref Vref
-
t
resettfeedthrough
Reference level
inm
"diff DSI" outm
outm
+
Vref
signal level
Charge dump
Requirements:
•
•
•
•
•
•
4 Clocks
5K
Clamp & Sample
~5nV / √Hz
500KHz Operation freq
.01% Crosstalk
Differential outputs
Output Drive > 50pF
Supply ±2.5V
1 Clock
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La Londe-les-Maures
october2009
4
ASPIC Layout
• First proto submited layout
4 DSI channels
4 C&S channels
Sefri Rachid @LPNHE
3.8mm
•Techno : CMOS 0.35µ 5V
•Vendor : AMS
•Package : CQFP100
La Londe-les-Maures
2.7mm
october2009
5
TESTS of ASPIC V1
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october2009
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COLD TESTS
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7
Power vs Temperature
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8
Offset vs. Temperature
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october2009
9
Proto 1 design
The first prototype has demonstrated
Comparison between DSI and C&S in same chip
DSI principle and multi channel IC feasibility at
low temperature with low crosstalk
Good fit between simulations and measurements
C&S feasibility
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La Londe-les-Maures
october2009
10
ASPIC:
nd
2
proto
 Technologie : AMS CMOS 0.35µ 5V
 8 Channel full DSI
 Package : CQFP100
8 Dual Slope Integrators
 3 input amplifier gains : 2.5 – 5 – 7.5
 to deal with CCD gain spread.
 3 integration time constants : 500ns – 1µs – 1.5µs
 to deal with CCD readout frequency.
Multi Gain
 Idle mode : DC current reduction by a factor of 1.000
baseline : { gain 5 + 500ns integration time}
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La Londe-les-Maures
october2009
11
Warm Test Stand
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Linearity
%
Residu
Gain 5 Linearity
0.15000
0.10000
0.05000
0.00000
0
50
100
150
200
250
300
350
400
Output (mV)
5000
y = 12.458x - 1.1182
4000
3000
2000
-0.05000
1000
-0.10000
0
0
dsi_c1 gain 5 It = 500ns T = 193K
100
200
300
400
-0.15000
input (mV)
Vin (mV)
%
Residu
Gain 7,5 Linearity
dsi_c1 gain 7.5 It = 500ns T = 193K
0.15
0.1
0.05
0
-0.05
0
50
100
150
200
250
300
-0.1
Output (mV)
0.2
5000
y = 16.604x + 0.4556
4000
3000
2000
1000
0
-0.15
0
Vin (mV)
100
200
300
input (mV)
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october2009
13
Main Improvement : noise
Noise simulations of ASPIC 2 @ -100°C
6µV RMS noise for a Time of Integration of 500ns
Proto 1 - Noise density simulations & Measurements
50
45
40
Noise vs 1/sqrt(Tint) @ -100°C
µV
35
30
Noise measurement LPNHE
9
25
Noise measurement LAL
8
20
Noise simulation
7
15
6
µV
10
5
R=5k - C=100pf
5
R=10k - C=100pf
4
0
0
0,05
0,1
1/SQRT(Tint)
2
1
Noise simulations and measurements of ASPIC 1
19µV RMS noise for a Time of Integration of 500ns
Input noise ( uV)
40
R=15k - C=100pf
3
0,15
0
0
0,01
0,02
0,03
0,04
0,05
0,06
1/sqrt(Tint)
Noise measurement of ASPIC 2 @ 20°C
Integration Time (ns)
35
30
25
20
15
10
5
0
0.044
0.05
0.057
1/sqrt(int)
0.07
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0.1
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Input Noise uV
500
9
400
10,6
300
13,2
200
17,61
100
33,5
october2009
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Crosstalk measurements @ 300K
The crosstalk of ASPIC02 is about 0,02 and 0,03%
(Adjacents channels)
Signal source -100mV pulse
The crosstalk between ch3 and ch5 is about
0,002 % and 0,008%
ΔV = Crosstalk
Adjacent channel output signal X 10
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15
LAL/LPNHE Cryostats
LAL cryostat
dedicated to
prototyping tests
LPNHE cryostat dedicated to
prototyping & pre-prod tests
Already cooled down – used for ASPIC1
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16
CLASSIC
•
•
•
•
8 channels Clamp & Sample chip
Pin to pin compatible with ASPIC 2
3 bit programmable gain input amplifier
4 bit programmable output time constant
filter to match the readout frequency
• Two differents C&S topologies
• Idle mode
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october2009
17
CLASSIC Schematic
New functionalities / ASPIC1:
Switched-capacitor gain
Programmable input gain amplifier
Programmable time constant filter
Two different C&S topologies:
1st :
One channel noise : 3.9 µV
18mW/channel and < 1% nonliearity
2nd
Positive gain channel noise : 2.81 µV
Negative gain channel noise : 2.47µV
18mW/channel and < 1% nonliearity
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DSI vs C&S
• Signal de sortie d’un CCD = signal de faible niveau:
 chaque photo-électron produira quelques µV.
• Forme du signal complexe – nécessité d’un timing précis
Vout
t
reset feedthrough
Reference level
Etage de sortie d’un CCD
signal level
Charge dump
Le traitement de l’image doit se faire en lisant le niveau de référence et le signal
La différence de ces signaux donnera le nombre d’électrons du pixel lu
Technique: Correlated Double Sampling
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october2009
DSI vs C&S
• Dual Slope Integrator
50ns
Reset CCD
50ns
Clamp
Reset int
DSI Switch
isolated Integration - Isol. Integration + isolated
150ns
850ns
150ns
850ns
Signal
ADC Sampling
2µs
DSI Timing proposal
xxxV
1us
150ns
1.15us
0V
int. rst
RST
CDD signal
-xxxV
-2.5V
– Suppression automatique du bruit de reset des CCD
– Utilisé dans SNAP: A low power, wide dynamic range multigain signal processor
for the SNAP CCD – JP Walder et Al. – NSS Oct 2004.
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october2009
2us
DSI vs C&S
• Clamp & Sample
50ns
Reset CCD
Clamp
CCD Signal
C&S Signal
DC restore
ADC Sampling
Switch de clamp
2µs
CnS Timing proposal
-
Le bruit CCD en kT/C est « clampé »
Simple – robuste – 1 seule horloge nécessaire – indépendant (jusqu’à une certaine limite!) de la
fréquence de lecture du CCD.
Utilisé pour la lecture des CCD de MegaCam (design du groupe électronique de l’IRFFU)
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La Londe-les-Maures
october2009
DSI vs C&S
Bruit
 On peut montrer que le bruit:
Bruit dominé par le bruit thermique haute
fréquence de l’étage d’entrée (pas d’intégration)
• du DSI est équivalent à
• du C&S est équivalent à
Bruit dominé par le bruit thermique du CCD (si un
étage de gain est placé avant l’intégration)
Où en = densité de bruit du CCD, S=gain du CCD, ∆T=temps d’intégration, τ=filtre du
C&S
Sefri Rachid @LPNHE
La Londe-les-Maures
october2009
Ampli Bloc
Sefri Rachid @LPNHE
La Londe-les-Maures
october2009
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