Transcript Front-end Electronics for the LHCb Preshower 1

Front-end Electronics for the LHCb
Preshower
Rémi CORNAT, Gérard BOHNER, Olivier DESCHAMPS, Jacques
LECOQ, Pascal PERRET
LPC Clermont-Ferrand
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Plan
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Introduction
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Front-end Electronics
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
Very front end
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Front end
Prototypes
R. CORNAT - LPC - LECC Colmar - septembre 2002
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The Preshower
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Located upstream from ECAL
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~6000 cells (same as ECAL)
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12 mm thick lead plane followed by scintillator pads
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Raw Signal
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We mostly have MIPs
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1 MIP signal is very erratic
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Longer than 25 ns
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~85 % during 1st period

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Dynamic range from 0 to 100 MIP
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Trigger at 5 MIP (5 % accuracy)
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10 bits
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Very Front-end Electronics
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Common mode to differential mode conversion
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Signal integration
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Within 25 ns periods
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Without dead-time
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16 half-channels per chip
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2 V amplitude
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Cable adaptation
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Standard CAT5+ Ethernet cable
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No individual but common shielding
Both sides adaptation
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Pole-zero correction
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No significant crosstalk
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Negligible reflected signal after 20 m long
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Front-end Electronics
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Mixed part
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Signal reception
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Levels adaptation
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Digitisation
Digital processing
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Physics data
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Trigger data : linked to SPD and ECAL
R. CORNAT - LPC - LECC Colmar - septembre 2002
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FEE : Mixed part
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Everything in differential mode from VFE to digitisation
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Cable adaptation
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Electrical levels matching
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From 1 V positive differential, -0.8 V CM to 1V bipolar differential,
0.5 V CM
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Op. Amp. AD8138 or AD8132
50 mV differential pedestal
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To cancel VFE offset
Low pass filter
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Noise reduction
R. CORNAT - LPC - LECC Colmar - septembre 2002
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FEE : Mixed part
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Digitisation : AD9203
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10 bits, 40 MHz, 75 mW,
differential inputs
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Package size fits requirements
(64 channels on the FE board)
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Vref feed-back from ADC
to Op. Amp.
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RJ 45 connector
R. CORNAT - LPC - LECC Colmar - septembre 2002
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FEE : Mixed part
R. CORNAT - LPC - LECC Colmar - septembre 2002
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FEE : Mixed part
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1 cm x 4 cm hierarchical element
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64 channels fit on a 9U board
Noise : from 0.8 mV to 0.4 mV
due to layout optimisation
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Ground plane
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Critical wires routing
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LVDS Clock
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Digital Processing
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Pedestal
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Gain
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Pile-up
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PMT signal longer than 25 ns
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Coding (float, 8b)
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Parameters per half channel
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128 half-channels per board
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Trigger data
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SPD data
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64 bits per FE board
Preshower : 1 bit per cell
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Threshold on PS processed data
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Trigger functions
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Trigger data = 1b (threshold)
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SPD data processing = count # hits in a 64 b data
block
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FPGA : 1 clk cycle
Neighbourhood search
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Dedicated prototype, tested and validated
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Trigger functions
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SPD data synchronization
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Time alignment with respect to PS data
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Multiplicity calculation on SPD data
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Neighbours fetch
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2x2 algorithm
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1 address per ECAL FE
board (half PS FE board)
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Send only useful data to
ECAL validation board
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Neighbours
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Process applied on both SPD and PS data
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Data multiplexed to outputs according to the address
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The structure for 1 half-board fits into an EPM3256
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tp@->out < 20 ns
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Low level vhdl model written
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Prototype tested
Will be fitted into ACTEL fpga
R. CORNAT - LPC - LECC Colmar - septembre 2002
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SPD
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SPD data synchronization
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Variable length pipe-line
Multiplicity calculation on SPD data
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Count # hits in a 64 bits data block
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Low level VHDL model written
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FPGA : one 40 MHz clock cycle (Altera ACEX)
R. CORNAT - LPC - LECC Colmar - septembre 2002
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FE boards synchronization
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Bordering cells data transmitted between PS FE
boards
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Latency for neighbours transmission depends on
data source
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Local board
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N, E board
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Corner board
Pipe-line stages added to compensate
R. CORNAT - LPC - LECC Colmar - septembre 2002
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FPGA based prototype
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16 channels = 2 VFE chips
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No TTC, no ECS
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Additional DAQ system
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FPGA internal memory
VME
Was used for test beam
with PS detector and VFE
chip prototypes
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FPGA based prototype
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DAQ channel : L0 pipe-line + RAM
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Up to 1024 samples per run (internal memory
limitation)
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Single and temporal modes
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Allows to acquire up to 32 successive samples per trigger
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Many process and acquisition parameters
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C++ software + ROOT graphical interface
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LabView version for debugging purpose
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Graphical interface
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Linux
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Statistical
analysis
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Can manage
many boards
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ASIC prototype
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4 channels (design is pad limited)
AMS 0.35 mm
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9 mm2
CQFP100 package
220 configuration bits through
a serial interface
 Parity check and triple voting on configuration data
 Will be tested soon
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R. CORNAT - LPC - LECC Colmar - septembre 2002
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Approximate cost
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4 channels = 1 ACEX1K or 1 9mm2 ASIC or ½ ACTEL SX32
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32 cm in height for 64 channels
Technology
ACEX1K100
ASIC 0.35 mm
ACTEL 54SX32
Ch. #, package
4 (6), QFP208
4, QFP100
2, QFP208
Cost/channel
10 EUR (/1000) + ECS
12 EUR (/2000) + test
18 EUR (/1000) + prog&test
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Foundry and design delays  subcontracted ACTEL prog.
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ASIC meets available space constraints on the board
R. CORNAT - LPC - LECC Colmar - septembre 2002
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Conclusion
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VFE + FE validated (test beam)
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Low noise for the analogue part
(Radiation and) surface use constraints
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Best candidate : ASIC
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Prototype board used for MAPMT characterization
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Final board
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Collaboration with LAL (Orsay) : DAQ, ECS, TTC parts
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