inst.eecs.berkeley.edu/~cs61c

CS61C : Machine Structures

Lecture #15 – Intro to Synchronous Digital Systems, State Elements I 2008-7-16 Go

BEARS~

CS61C L15 Intro to SDS, State Elements I (1) Albert Chae, Instructor Chae, Summer 2008 © UCB

What are “Machine Structures”?

Software Application (Netscape) Compiler Assembler Operating System (MacOS X) 61C Hardware Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors Instruction Set Architecture Coordination of many

levels of abstraction

ISA is an important abstraction level: contract between HW & SW Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (2)

Below the Program

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High-level language program (in C) swap int v[], int k){ int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; }

C compiler •

Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4,$2 lw lw $15, 0($2) $16, 4($2) sw sw jr $16, 0($2) $15, 4($2) $31

assembler •

Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 . . .

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (3)

61C Levels of Representation High Level Language Program (e.g., C) temp = v[k]; v[k] = v[k+1]; v[k+1] = temp;

Compiler

Assembly Language Program (e.g.,MIPS)

Assembler

Machine Language Program (MIPS)

Machine Interpretation

Hardware Architecture Description (Logic, Logisim, etc.) lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2)

0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

Architecture Implementation

Logic Circuit Description (Logisim, etc.) Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (4)

Synchronous Digital Systems

The hardware of a processor, such as the MIPS, is an example of a Synchronous Digital System

Synchronous:

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Means all operations are coordinated by a central clock .

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It keeps the “heartbeat” of the system!

Digital:

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Mean all values are represented by discrete values

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Electrical signals are treated as 1’s and 0’s and grouped together to form words.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (5)

Logic Design

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Next 4 weeks: we’ll study how a modern processor is built; starting with basic elements as building blocks.

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Why study hardware design?

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Understand capabilities and limitations of hardware in general and processors in particular.

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What processors can do fast and what they can’t do fast (avoid slow things if you want your code to run fast!)

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Background for more detailed hardware courses (CS 150, CS 152, EE 192)

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There is just so much you can do with processors. At some point you may need to design your own custom hardware.

CS61C L15 Intro to SDS, State Elements I (6) Chae, Summer 2008 © UCB

PowerPC Die Photograph Let’s look closer… CS61C L15 Intro to SDS, State Elements I (7) Chae, Summer 2008 © UCB

Transistors 101

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MOSFET

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Metal-Oxide-Semiconductor Field-Effect Transistor

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Come in two types: G D G S

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n-type NMOSFET p-type PMOSFET

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For n-type ( p-type opposite) n-type

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If voltage not enough between G & S, transistor turns “off” (cut-off) and Drain-Source NOT connected S

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If the G & S voltage is high enough, transistor turns “on” (saturation) and Drain-Source ARE connected p-type Side view D www.wikipedia.org/wiki/Mosfet CS61C L15 Intro to SDS, State Elements I (8) Chae, Summer 2008 © UCB

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Transistor Circuit Rep. vs. Block diagram Chips is composed of nothing but transistors and wires.

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Small groups of transistors form useful building blocks.

“1” (voltage source) a b c 0 0 0 1 1 0 1 1 1

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1 1 0 “0” (ground) Block are organized in a hierarchy to build higher-level blocks: ex: adders.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (9)

Signals and Waveforms: Clocks

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Signals

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When digital is only treated as 1 or 0

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Is transmitted over wires continuously

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Transmission is effectively instant

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Implies that any wire only contains 1 value at a time Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (10)

Signals and Waveforms CS61C L15 Intro to SDS, State Elements I (11) Chae, Summer 2008 © UCB

Signals and Waveforms: Grouping CS61C L15 Intro to SDS, State Elements I (12) Chae, Summer 2008 © UCB

Signals and Waveforms: Circuit Delay

2 3 5 3 4 7 4 5 5 6 9 11

CS61C L15 Intro to SDS, State Elements I (13) Chae, Summer 2008 © UCB

Type of Circuits

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Synchronous Digital Systems are made up of two basic types of circuits:

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Combinational Logic (CL) circuits

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Our previous adder circuit is an example.

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Output is a function of the inputs only.

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Similar to a pure function in mathematics, y = f(x). (No way to store information from one invocation to the next. No side effects)

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State Elements : circuits that store information.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (14)

Circuits with STATE (e.g., register) CS61C L15 Intro to SDS, State Elements I (15) Chae, Summer 2008 © UCB

Peer Instruction A. SW can peek at HW (past ISA abstraction boundary) for optimizations B. SW can depend on particular HW implementation of ISA AB 0 : FF 1 : F T 2 : T F 3 : TT C. Timing diagrams serve as a critical debugging tool in the EE toolkit White is true C: T F Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (16)

Sample Debugging Waveform CS61C L15 Intro to SDS, State Elements I (17) Chae, Summer 2008 © UCB

Administrivia

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Hw3 is due today

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Proj2 is due Friday

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Faux midterm today 6-9

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Review session Thursday in lecture

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Extra MT OH?

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Midterm 7/21 7-10p in 155 Dwinelle Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (18)

Uses for State Elements 1. As a place to store values for some indeterminate amount of time:

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Register files (like $1-$31 on the MIPS) Memory (caches, and main memory) 2. Help control the flow of information between combinational logic blocks.

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State elements are used to hold up the movement of information at the inputs to combinational logic blocks and allow for orderly passage.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (19)

Accumulator Example

Why do we need to control the flow of information?

Want: S=0; for (i=0;i

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Each X value is applied in succession, one per cycle.

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After n cycles the sum is present on S.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (20)

First try…Does this work?

Feedback Nope!

Reason #1… What is there to control the next iteration of the ‘ for ’ loop?

Reason #2… How do we say: ‘ S=0 ’?

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (21)

Second try…How about this?

Rough timing…

Register is used to hold up the transfer of data to adder.

CS61C L15 Intro to SDS, State Elements I (22) Chae, Summer 2008 © UCB

Register Details…What’s inside?

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n instances of a “Flip-Flop”

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Flip-flop name because the output flips and flops between and 0,1

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D is “data”, Q is “output”

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Also called “d-type Flip-Flop” Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (23)

What’s the timing of a Flip-flop? (1/2)

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Edge-triggered d-type flip-flop

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This one is “positive edge-triggered”

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“On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”

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Example waveforms: Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (24)

What’s the timing of a Flip-flop? (2/2)

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Edge-triggered d-type flip-flop

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This one is “positive edge-triggered”

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“On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”

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Example waveforms (more detail): Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (25)

Accumulator Revisited (proper timing 1/2)

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Reset input to register is used to force it to all zeros (takes priority over D input).

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S i-1 holds the result of the i th -1 iteration.

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Analyze circuit timing starting at the output of the register.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (26)

Accumulator Revisited (proper timing 2/2)

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reset signal shown.

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Also, in practice X might not arrive to the adder at the same time as S i-1

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S i temporarily is wrong, but register always captures correct value.

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In good circuits, instability never happens around rising edge of clk.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (27)

Recap of Timing Terms

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Clock (CLK) - steady square wave that synchronizes system

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Setup Time - when the input must be stable before the rising edge of the CLK

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Hold Time - when the input must be stable after the rising edge of the CLK

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“CLK-to-Q” Delay - how long it takes the output to change, measured from the rising edge

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Flip-flop - one bit of state that samples every rising edge of the CLK

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Register - several bits of state that samples on rising edge of CLK or on LOAD Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (28)

Finite State Machines (FSM) Introduction

• You have seen FSMs in other classes.

• Same basic idea.

• The function can be represented with a “state transition diagram”.

• With combinational logic and registers, any FSM can be implemented in hardware.

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (29)

Finite State Machine Example: 3 ones…

FSM to detect the occurrence of 3 consecutive 1’s in the input.

Draw the FSM…

Assume state transitions are controlled by the clock: on each clock cycle the machine checks the inputs and moves to a new state and produces a new output…

CS61C L15 Intro to SDS, State Elements I (30) Chae, Summer 2008 © UCB

Hardware Implementation of FSM

… Therefore a register is needed to hold the a representation of which state the machine is in. Use a unique bit pattern for each state.

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Combinational logic circuit is used to implement a function maps from

present state and input

to

next state and output.

CS61C L15 Intro to SDS, State Elements I (31) = ?

Chae, Summer 2008 © UCB

Hardware for FSM: Combinational Logic

Next lecture we will discuss the detailed implementation, but for now can look at its functional specification, truth table form .

PS 00 00 01 01 10 10

Truth table…

Input 0 1 0 1 0 1 NS 00 01 00 10 00 00 Output 0 0 0 0 0 1

Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (32)

Peer Instruction A. HW feedback akin to SW recursion B. The minimum period of a usable synchronous circuit is at least the CLK-to-Q delay AB 0 : FF 1 : F T 2 : T F 3 : TT C. You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input. CS61C L15 Intro to SDS, State Elements I (33) White is true C: T F Chae, Summer 2008 © UCB

Conclusion

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ISA is very important abstraction layer

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Contract between HW and SW

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Clocks control pulse of our circuits

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Voltages are analog, quantized to 0/1

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Circuit delays are fact of life

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Two types of circuits:

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Stateless Combinational Logic (&,|,~)

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State circuits (e.g., registers) Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (35)

“And In conclusion…”

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State elements are used to:

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Build memories

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Control the flow of information between other state elements and combinational logic

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D-flip-flops used to build registers

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Clocks tell us when D-flip-flops change

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Setup and Hold times important

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Finite State Machines extremely useful

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You’ll see them again (150,152), 164, 172, 174, etc Chae, Summer 2008 © UCB CS61C L15 Intro to SDS, State Elements I (36)