Transcript ECE 448 Lecture 16 Features of Modern FPGAs ECE 448 – FPGA and ASIC Design with VHDL George Mason University.

ECE 448
Lecture 16
Features of Modern FPGAs
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Resources
Clive “Max” Maxfield,
The Design Warrior’s Guide to FPGAs,
Elsevier, 2004.
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Resources
Xcell Journal
available for FREE on line @
http://www.xilinx.com/publications/xcellonline/
FPGA and Structured ASIC Journal
available for FREE by e-mail or on the web @
http://www.fpgajournal.com/
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Xilinx FPGA Families
•
•
•
Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern
designs.
High-performance families
• Virtex (220 nm)
• Virtex-E, Virtex-EM (180 nm)
• Virtex-II (130 nm)
• Virtex-II PRO (130 nm)
• Virtex-4 (90 nm)
• Virtex-5 (65 nm)
• Virtex-6 (40 nm) coming in 2009
Low Cost Family
• Spartan/XL – derived from XC4000
• Spartan-II – derived from Virtex
• Spartan-IIE – derived from Virtex-E
• Spartan-3 (90 nm)
• Spartan-3E (90 nm) – logic optimized
• Spartan-3A (90 nm) – I/O optimized
• Spartan-3AN (90 nm) – non-volatile,
• Spartan-3A DSP (90 nm) – DSP optimized
• Spartan-6 (45 nm) – coming in 2009
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Field Programmable
Gate Arrays
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General structure of an FPGA
Programmable
interconnect
Programmable
logic blocks
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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Xilinx CLB
Configurable logic block (CLB)
CLB
CLB
CLB
CLB
Slice
Slice
Logic cell
Logic cell
Logic cell
Logic cell
Slice
Slice
Logic cell
Logic cell
Logic cell
Logic cell
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Devices, Tools, and Flows. ISBN 0750676043
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Simplified view of a Xilinx Logic Cell
16-bit SR
16x1 RAM
a
b
c
d
4-input
LUT
e
y
mux
flip-flop
q
clock
clock enable
set/reset
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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4-bit LUTs vs. 6-bit LUTs
6-bit LUTs introduced in Virtex 5
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RAM Blocks and Multipliers in Xilinx
FPGAs
RAM blocks
Multipliers
Logic blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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DSP Blocks
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Multiplier-Accumulator - MAC
Multiplier
Adder
Accumulator
A[n:0]
x
B[n:0]
+
MAC
Y[(2n - 1):0]
The Design Warrior’s Guide to FPGAs
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Xilinx XtremeDSP
• Starting with Virtex 4 family, Xilinx introduced DSP48 block
for high-speed DSP on FPGAs
• Essentially a multiply-accumulate core with many other
features
• Now also Spartan-3A and Virtex 5 have DSP blocks
13
DSP48 Slice: Virtex 4
14
DSP48 Functionality
•
•
The math portion of the DSP48 slice consists of an 18-bit x 18-bit, two’s complement multiplier followed by
three 48-bit datapath multiplexers (with outputs X, Y, and Z) followed by a three-input, 48-bit
adder/subtracter.
The data and control inputs to the DSP48 slice feed the arithmetic portions directly or are optionally
registered one or two times to assist the construction of different, highly pipelined, DSP application
solutions.
•
•
•
•
Full speed operation is 500 MHz when using the pipeline registers
Equation 1-1 summarizes the combination of X, Y, Z, and CIN by the adder/subtracter.
•
•
•
•
The CIN, X multiplexer output, and Y multiplexer output are always added together.
This combined result can be selectively added to or subtracted from the Z multiplexer output.
Adder Out = (Z ± (X + Y + CIN))
Equation 1-1
Equation 1-2 describes a typical use where A and B are multiplied, and the result is added to or subtracted
from the C register. Selecting the multiplier function consumes both X and Y multiplexer outputs to feed the
adder.
•
•
•
The data inputs A and B can be registered once or twice
The other data inputs and the control inputs can be registered once.
The two 36-bit partial products from the multiplier are sign extended to 48 bits before being sent to the
adder/subtracter.
Adder Out = C ± (A × B + CIN)
Equation 1-2
Figure 1-4 shows the DSP48 slice in a very simplified form. The seven OPMODE bits control the selection
of the 48-bit datapaths of the three multiplexers feeding each of the three inputs to the adder/subtracter. In
all cases, the 36-bit input data to the multiplexers is sign extended, forming 48-bit input datapaths to the
adder/subtracter.
•
Based on 36-bit operands and a 48-bit accumulator output, the number of “guard bits” (i.e., bits available to guard
against overflow) is 12. Therefore, the number of multiply accumulations possible before overflow occurs is 4096.
Combinations of OPMODE, SUBTRACT, CARRYINSEL, and CIN control the function of the adder/subtracter.
Source: Xilinx 15
Simplified Form of DSP48
16
Mathematical Functions
• DSP 48 can perform mathematical functions such as:
•
•
•
•
•
•
•
•
•
Add/Subtract
Accumulate
Multiply
Multiply-Accumulate
Multiplexer
Barrel Shifter
Counter
Divide (multi-cycle)
Square Root (multi-cycle)
• Can also create filters such as:
•
•
•
•
Serial FIR Filter (Xilinx calls this MACC filters)
Parallel FIR Filter
Semi-Parallel FIR Filter
Multi-rate FIR Filters
17
DSP48E Slice : Virtex5
18
Xilinx DSP48
19
Clock Managers
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A simple clock tree
Clock
tree
Flip-flops
Special clock
pin and pad
Clock signal from
outside world
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Devices, Tools, and Flows. ISBN 0750676043
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Clock Manager
Clock signal from
outside world
Clock
Manager
etc.
Daughter clocks
used to drive
internal clock trees
or output pins
Special clock
pin and pad
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Jitter
1
2
3
4
Ideal clock signal
Real clock signal with jitter
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Superimposed cycles
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Removing Jitter
Clock signal from
outside world
with jitter
Clock
Manager
etc.
“Clean” daughter
clocks used to drive
internal clock trees
or output pins
Special clock
pin and pad
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Frequency Synthesis
1.0 x original clock frequency
2.0 x original clock frequency
.5 x original clock frequency
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Phase shifting
0o Phase shifted
90o Phase shifted
180o Phase shifted
270o Phase shifted
Figure 4-20
ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
26
Removing Clock Skew
Daughter clock (monitored
downstream of the clock manager)
fed back to special input
Clock signal from
outside world
De-skewed daughter
clocks used to drive
internal clock trees
or output pins
Special clock
pin and pad
1
2
3
4
Main (mother) clock
1
2
3
4
Untreated daughter clock
1
2
3
De-skewed daughter clock
The Design Warrior’s Guide to FPGAs
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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Supply Voltage
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Change in Supply Voltages
Year
1998
1999
2000
2001
2003
2008
2009
TechnologyCore Supply Voltage (V)
350
3.3
250
2.5
180
1.8
150
1.5
130
1.2
65
1.0
40
0.9
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General-Purpose I/O
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General-Purpose IO Blocks
1
0
2
7
General-purpose I/O
banks 0 through 7
3
6
4
5
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Parallel I/O Standards supported by Virtex 5
LVCMOS (3.3v, 2.5v, 1.8v, 1.5v, and 1.2v)
LVDS, Bus LVDS, Extended LVDS
LCPECL
PCI, PCI-X
HyperTransport (LDT)
HSTL (1.8v, 1.5v, Classes I, II, III, IV)
HSTL_I_12 (unidirectional only)
DIFF_HSTL_I_18, DIFF_HSTL_I_18_DCI
DIFF_HSTL_I, DIFF_HSTL_I_DCI
RSDS_25 (point-to-point)
SSTL (2.5v, 1.8v, Classes I, II)
DIFF_SSTL_I
DIFF_SSTL2_I_DCI
DIFF_SSTL18_I, DIFF_SSTL18_I_DCI
GTL, GTL+
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Serial I/O Standards supported by Virtex 5
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Gigabit Transceivers
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Using High-Speed Tranceivers to
Communicate Between Devices
Transceiver block
Differential pairs
FPGA
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Using a Bus to Communicate
Between Devices
n-bit bus
FPGA
Other
device
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Using High-Speed Tranceivers to
Communicate Between Devices
Transceiver block
FPGA
Transmit (TX) to other device
Receive (RX) from other device
Differential
pairs
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Effect of Noise on Single Wire
and Differential Pair
Noise spikes
(a)
Outside
World
FPGA
(b)
1
IN
IN
Standard
Input
RXN
Differential
Pair
0
Noise spikes
RXN 1
RXP
RXP 0
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Generating a Differential Pair
Transmitting
Device
Outside
World
TXN
TXP
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Multiple Standards for High-Speed Serial
Communication
Fibre Channel
InfiniBand
PCI Express (developed by Intel)
RapidIO
SkyRail (developed by MindSpeed Technologies)
10-gigabit Ethernet
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Using FPGA to Interface Between
Multiple Standards
Gigibit interface
standard A
Transceiver
blocks
Gigibit interface
standard B
“Stuff”
Chip A
FPGA
Chip B
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An Ideal Signal vs. Signal Seen by Receiver
1
0
1
0
1
0
1
0
1
Signal sent from
transmitter
Signal “seen”
by receiver
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The Effects of Transmitting a Series of
Identical Bits
1
1
1
0
1
0
1
0
1
Signal sent from
transmitter
Signal “seen”
by receiver
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Main Elements of the Transceiver Block
8b/10b
Encoder
FIFO
Polarity
flipper
Serializer
TXP
8-bit bus
from main
FPGA fabric
TXN
This is where
pre-emphasis
takes place
Transmitter
FIFO
8b/10b
Deccoder
Polarity
flipper Deserializer
This is where
equalization
takes place
RXP
8-bit bus
to main
FPGA fabric
To
another
device
RXN
From
another
device
Receiver
Transceiver Block
FPGA
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Ganging Multiple Transceivers Together
Four gigabit
transceiver
blocks
4x electrical differential
signal TX and RX pairs at
2.5 gigabits/second each
To/from
the main
FPGA fabric
FPGA
Special external
interface chip
Channel bonding
control signals
Optical cable/signal
(10 gigabits/second)
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Pre-emphesis and Equalization
Transceiver
Pre-emphasis
applied to outputs
Equalization
applied to inputs
Chip A
Transceiver
CHIP B
Equalization
applied to inputs
Pre-emphasis
applied to outputs
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Recovering Clock Signal
1
0
1
0
1
0
1
0
1
0
1
0
(a) Simple signal
Real edges
1
1
1
0
0
0
1
0
1
1
0
1
(b) More complex signal
Derived edges
Real edges
47
Sampling the Incoming Signal
Data sample times
Derived edges
Real edges
48
The Effect of Jitter
Cycle 1
Cycle 2
Cycle 3
Cycle 4
(a) Ideal signal
(b) With jitter
(c) Cycle 1
(d) 1 & 2
(e) 1 & 2 & 3
(f) 1 & 2 & 3 & 4
(g) “Folded”
49
Eye Diagram and Eye Mask
Eye Mask
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Embedded Microprocessors
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Embedded Microprocessor Cores
uP
uP
uP
uP
uP
(a) One embedded core
(b) Four embedded cores
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Virtex-II Pro Architecture
2
3
Features:
1.
2.
3.
4.
5.
6.
Processor Block
RocketIO Multi-Gigabit
Transceivers
CLB and Configurable Logic
SelectIO-Ultra
Digital Clock Managers
Multipliers and Block
SelectRAM
1
6
4
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53
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Processor Block
• Contains four components:
BRAM
• Processor Local Bus (PLB)
• On-chip Peripheral Bus (OPB)
• Device Control Register
(DCR) Bus
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Control
PPC 405
Core
Interface Logic
BRAM
FPGA CLB Array
• IBM CoreConnect Bus
Architecture Features:
BRAM
OCM Controller
OCM Controller
• Embedded IBM PowerPC
405-D5 RISC CPU core
• On-Chip Memory (OCM)
controllers and interface
• Clock/control interface logic
• CPU-FPGA Interfaces
BRAM
55
PowerPC Cores
PowerPC
System
PowerPC
System
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Embedded Development Kit (EDK)
Software Flow
Hardware Flow
Processor IP,
Microprocessor
Peripheral
Description Files
VHDL /
Verilog
C / C++
Code
Libraries
PlatGen
Synthesizer
Compiler
LibGen
Microprocessor
Hardware
Specification
File
EDIF IP
Netlists
Object Files
Microprocessor
Software
Specification File
ISE /
Xflow
Linker
System
Constraint
File
Bitstream
Data2MEM
Executable
Download to FPGA
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Configuration of FPGAs
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Static RAM-based Technology
SRAM
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SRAM FPGA Configuration
•
Loading the bitstream into internal memory by delivering it through one of the
configuration interfaces
•
Configuration phases:
1.
2.
3.
4.
Clearing the configuration memory
Initialization
Bitstream loading
Device startup
Configuration Device
Bitstream
A series of
command
and data
101110
101011
100101
001010
011101
SRAM FPGA
• JTAG
• SelectMAP
• Slave/Master Serial
• ICAP
Correspond to
configuration modes
Configuration
Interface
Configuration
Logic
Configuration
Memory
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Configuration of SRAM based FPGAs
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
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FPGA Configuration Modes
Mode Pins
Mode
0
0
0
Serial load with FPGA as master
0
0
1
Serial load with FPGA as slave
0
1
0
Parallel load with FPGA as master
0
1
1
Parallel load with FPGA as slave
1
x
x
Use only the JTAG port
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Serial Load with FPGA as a Master
FPGA
Memory
Device
Control
Configuration data in
Cdata In
Cdata Out
Configuration
data out
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Daisy-Chaining FPGAs
Memory
Device
Control
FPGA
FPGA
Cdata In
Cdata In
Cdata Out
Cdata Out
etc.
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Parallel Load with FPGA as a Master
(off-the-shelf memory)
Memory
Device
Control
FPGA
Address
Configuration data [7:0]
Cdata In[7:0]
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Parallel Load with FPGA as a Master
(special-purpose memory)
Memory
Device
Control
Configuration data [7:0]
FPGA
Cdata In[7:0]
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Microprocessor
Peripheral,
Port, etc.
Memory
Device
Parallel Load with FPGA as a Slave
Control
Address
FPGA
Data
Cdata In[7:0]
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Using the JTEG Port
JTEG = Joint Test Action Group, IEEE 1149.1
JTAG data out
JTAG data in
From previous
JTAG filp-flop
To internal
logic
Input pad
Input pin from
outside world
JTAG flip-flops
From internal
logic
To next
JTAG filp-flop
Output pin to
outside world
Output pad
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Internal Processor Boundary Scan Chain
JTAG data out
JTAG data in
FPGA
Primary scan chain
Internal (core) scan chain
Core
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Reconfiguration Interfaces in Xilinx FPGAs
Internal Port
ICAP
(Virtex-II)
JTAG
SelectMap
(8 bits Parallel)
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Configuration times
of selected FPGA
devices
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