ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 5: September 9, 2013 Transistor Introduction (first order) 1 Penn ESE370 Fall2013 -- DeHon

Today • First order model • There are always Rs and Cs Penn ESE370 Fall2013 -- DeHon 2

Previously • Quasi-Static – inputs transition, circuit responds, and settles – Dynamic transition to roughly static states • DC/Steady-State – Ignore the capacitors • Zeroth-order allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits 3 Penn ESE370 Fall2013 -- DeHon

Zero-th Order MOSFET • Ideal Switch Vgs > Vth  conducts Vgs < Vth  does not conduct Vth – threshold voltage • Gate draws no current from input – Loads input capacitively Penn ESE370 Fall2013 -- DeHon 4

Zero-th Order MOSFET I DS Penn ESE370 Fall2013 -- DeHon 5

First Order Model • Switch – Loads gate input capacitively • C g – Has finite drive strength • R on Penn ESE370 Fall2013 -- DeHon 6

Gate Output • Assume this is equivalent circuit for gate output state Penn ESE370 Fall2013 -- DeHon 7

Gate Output Load • What is Vout if gate is unloaded?

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Gate Output Load • What happens to Vout when add a load?

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Resistive Load • What happens when load is resistance?

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Resistive Load • If loaded resistively, and resistive load is too strong (resistance too low) • Cause output voltage to drop 11 Penn ESE370 Fall2013 -- DeHon

Capacitive Load • What happens when load is capacitance?

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Capacitive Load • Capacitive load does not change the steady-state output voltage • Will effect the delay (settling time) Penn ESE370 Fall2013 -- DeHon 13

First Order Model • Switch – Loads gate input capacitively • Draw no current • Does not impact steady-state voltage • Impacts Delay – Has finite drive strength • Could form voltage divider with resistive load • Impacts Delay Penn ESE370 Fall2013 -- DeHon 14

First Order Model (vs. Vds) Penn ESE370 Fall2013 -- DeHon 15

First Order Model (vs. Vgs) Penn ESE370 Fall2013 -- DeHon 16

Refine to First Order Penn ESE370 Fall2013 -- DeHon 17

Zero-th Order Tells us how switches set (Vin=0) How are switches set in this case?

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Zero-th Order Tells us how switches set (Vin=0) V2=Vdd Vout=0 19 Penn ESE370 Fall2013 -- DeHon

Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall2013 -- DeHon V2=Vdd Vout=0 20

Zero-th Order Tells us how switches set (Vin=0) • Leaves an RC Circuit we can analyze ESE215 problem 21 Penn ESE370 Fall2013 -- DeHon

Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is equivalent circuit of load at V2?

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Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is equivalent output circuit for first pair of transistors driving V2?

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Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is relevant circuit?

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Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) Vdd What is relevant circuit?

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Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) Penn ESE370 Fall2013 -- DeHon What is delay of this stage?

(charging V2 when Vin switch Vdd  0) 26

What more does first-order model tell us?

• Delay • Quasistatic behavior • Voltage settling with resistive loads – At least some basis for reasoning Penn ESE370 Fall2013 -- DeHon 27

What is this leaving out?

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What is this leaving out?

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What leaving out?

• What happens at intermediate voltages – Not rail-to-rail (not just gnd or Vdd input) • Details of dynamics, including… – Input not transition as step – Intermediate drive strengths change with Vgs • Isn’t really 0 current below threshold 30 Penn ESE370 Fall2013 -- DeHon

Engineering Control • Vth – process engineer • Drive strength (R on ) – circuit engineer control with sizing transistors • Supply voltages (Vdd) – range set by process – detail use by circuit design Penn ESE370 Fall2013 -- DeHon 31

Engineering Control: Threshold Penn ESE370 Fall2013 -- DeHon 32

Engineering Control: Drive Strength Penn ESE370 Fall2013 -- DeHon 33

Penn ESE370 Fall2013 -- DeHon Rs and Cs 34

Wire Capacitance Penn ESE370 Fall2013 -- DeHon 35

Wire Capacitance Penn ESE370 Fall2013 -- DeHon

C

 

r

 0

A d

36 

Penn ESE370 Fall2013 -- DeHon Wire Resistance 37

Wire Resistance Penn ESE370 Fall2013 -- DeHon

R

 

L A

38 

 Wire Resistance • Sanity check – Wire twice as long = resistors in series – Wire twice as wide = resistors in parallel

R

 

L A

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There are always Rs and Cs • Every wire (connection) has resistance • Every wire has capacitance • (Every wire has inductance) • Modeling vs. discrete components • Dominant effects – Rbig + Rsmall ≈ Rbig (Rwire << Ron)?

– Cbig || Csmall ≈ Cbig (Cwire<

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Big Ideas • MOSFET Transistor as switch • Purpose-driven simplified modeling – Aid reasoning, sanity check, simplify design • Analysis methodology – zero-th order to understand switch state (logic) – First-order to get equivalent RC circuit (delay) • New perspective on Rs and Cs 41 Penn ESE370 Fall2013 -- DeHon

MOSFET Penn ESE370 Fall2013 -- DeHon 42

Admin • Normal Office Hours this week – Spencer on Monday 5-6 (Detkin) • Finish up lab if have not already done so – Andre on Tuesday 4:15—5:30pm – Spencer on Wednesday 5-6 (Detkin) • Lecture on Wed.

• Homework on Thursday • Lab on Friday (Ketterer) Penn ESE370 Fall2013 -- DeHon 43