ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 8: September 16, 2013 Delay and RC Response Penn ESE370 Fall2013 -- DeHon.
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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 8: September 16, 2013 Delay and RC Response 1 Penn ESE370 Fall2013 -- DeHon Delay is RC Charging 2 Penn ESE370 Fall2013 -- DeHon Delay is RC Charging Strategy • Understand switch state • Break into stages • For each stage – Understand Rdrive – Understand Cload 3 Penn ESE370 Fall2013 -- DeHon Today • • • • • RC Charging RC Step Response What is the C? What is the R? Measuring Delay 4 Penn ESE370 Fall2013 -- DeHon 90% Rise Time? 5 Penn ESE370 Fall2013 -- DeHon What does response look like? Penn ESE370 Fall2013 -- DeHon about 2ps for 90% rise 6 Governing Equations? (KCL) • KCL @ Vmeasure? • Current across Resistor? • Current into Capacitor? 7 Penn ESE370 Fall2013 -- DeHon Equations Vin Vmeasure C dVmeasuredt R Vin Vmeasure dVmeasure dt RC 8 Penn ESE370 Fall2013 -- DeHon Solve Vmeasure dVmeasure Vin Vmeasure dt RC What’s Vmeasure? t Vmeasure Vin1 e RC 9 Penn ESE370 Fall2013 -- DeHon What does look like? V(t) 1 e t /(RC) V 10 Penn ESE370 Fall2013 -- DeHon Fillin on board Shape of Curve x e-x 1-e-x 0 0.1 1 2 2.3 V(t) 1 e Penn ESE370 Fall2013 -- DeHon t /(RC) V 11 Shape of Curve x e-x 1-e-x 0 0.1 1 2 2.3 1 0.9 1/e = 0.37 1/e2 = 0.14 0.1 0 0.1 0.66 0.86 0.9 V(t) 1 e Penn ESE370 Fall2013 -- DeHon t /(RC) V 12 Risetime: 10—90% Penn ESE370 Fall2013 -- DeHon Trise ~= 2.2ps 13 What is C? 14 Penn ESE370 Fall2013 -- DeHon Capacitance • • • • Wire MOSFET gate Logical Gate Fanout -- Total gate load 15 Penn ESE370 Fall2013 -- DeHon First Order Model • Switch – Loads input capacitively • As dig in, understand: – Origin of capacitance – How can we engineer – Tradeoffs 16 Penn ESE370 Fall2013 -- DeHon Logic Gate Input Capacitance • Capacitance on – A input? – B input? 17 Penn ESE370 Fall2013 -- DeHon Fanout • Number of things to which a gate output connects 18 Penn ESE370 Fall2013 -- DeHon Fanout in Circuit • Output routed to many gate inputs 19 Penn ESE370 Fall2013 -- DeHon Fanout in Circuit • Maximum fanout? • Second? • Min? 20 Penn ESE370 Fall2013 -- DeHon Lumped Capacitive Load Cload C gi ifanout C wi iwires 21 Penn ESE370 Fall2013 -- DeHon What is R? 22 Penn ESE370 Fall2013 -- DeHon Resistance • Wire resistance – Supply to transistor source – Transistor output gate it is driving • Transistor equivalent resistance 23 Penn ESE370 Fall2013 -- DeHon First Order Model • Switch – Resistive driver • As dig in, understand: – More sophisticated view – How can we engineer – Tradeoffs 24 Penn ESE370 Fall2013 -- DeHon Equivalent Resistance • What resistances might transistors contribute? – How many cases? – Assume Ron same all tr, Resistance of each? 25 Penn ESE370 Fall2013 -- DeHon Equivalent Resistance • What resistances might transistors contribute? Input 00 01 Rout Ron/2 Ron 10 11 Ron 2Ron 26 Penn ESE370 Fall2013 -- DeHon Rise/Fall • Rise and Fall time may differ – Why? – What is ratio? Input 00 01 Rout Ron/2 Ron 10 11 Ron 2Ron 27 Penn ESE370 Fall2013 -- DeHon Lumped Resistive Source Rdrive Rtrnet R wi Rpwr iwires Rtrnet = parallel and series combination of Rtr 28 Penn ESE370 Fall2013 -- DeHon Measuring Delay 29 Penn ESE370 Fall2013 -- DeHon Measuring Gate Delay • Next stage starts to switch before first finishes • Measure 50%--50% 67ps 80ps tdel = 13ps Penn ESE370 Fall2013 -- DeHon 30 Characterizing Gate/Technology • Delay measure will be – Function of load on gate – Function of input rise time • Which, in turn, may be a function of input loading 31 Penn ESE370 Fall2013 -- DeHon Delay vs. Risetime 1ps rise 10ps delay 100ps rise 20ps delay (if didn’t know input rise, wouldn’t know what a 13ps delay meant) Penn ESE370 Fall2013 -- DeHon 32 Characterizing Gate/Technology • Delay measure will be – Function of load on gate – Function of input rise time • Which, in turn, may be a function of input loading • Want to understand typical – At least comparable 33 Penn ESE370 Fall2013 -- DeHon Standard Measurement for Characterization • Drive with a gate – Not an ideal source – Input rise time typically would see in circuit • Measure loaded gate – Typical loading – FO4 34 Penn ESE370 Fall2013 -- DeHon HW2 Recommendation 35 Penn ESE370 Fall2013 -- DeHon Measurement for Characterization • Drive with a gate – Not an ideal source (how change if drive ideal?) – Input rise time typically would see in circuit • Measure loaded gate – Typical loading – FO4 36 Penn ESE370 Fall2013 -- DeHon Measurement for Characterization • Drive with a gate – Not an ideal source – Input rise time typically would see in circuit • Measure loaded gate – Typical loading – FO4 (how change unloaded?) 37 Penn ESE370 Fall2013 -- DeHon Delay is RC Charging 38 Penn ESE370 Fall2013 -- DeHon Admin • ngspice – Should work on eniac, ketterer machines now – Good to get running on laptop • 3 Lecture Week (all here) • Spencer Office Hours – Today – 11am (already happened..) – Tuesday extra 2pm in Ketterer – Wed. 6pm • Andre Office Hour – Tuesday 4:15pm Penn ESE370 Fall2013 -- DeHon 39