24th International Conference on Infrared and Millimeter Waves Submicron Transferred-Substrate Heterojunction Bipolar Transistors M Rodwell , Y Betser,Q Lee, D Mensa, J Guthrie, S Jaganathan,
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24th International Conference on Infrared and Millimeter Waves Submicron Transferred-Substrate Heterojunction Bipolar Transistors M Rodwell , Y Betser,Q Lee, D Mensa, J Guthrie, S Jaganathan, T Mathew, P Krishnan, S Long University of California, Santa Barbara SC Martin, RP Smith, NASA Jet Propulsion Labs Supported by ONR (M Yoder, J Zolper, D Van Vechten), AFOSR ( H Schlossberg ) Why are HEMTs smaller & faster than HBTs ? FETs have deep submicron dimensions. 0.1 µm HEMTs with 400 GHz bandwidths (satellites). 5 million 1/4-µm MOSFETs on a 200 MHz, $500 CPU. FET lateral scaling decreases transit times. FET bandwidths then increase. HBTs have ~1 µm junctions. vertical scaling decreases electron transit times. vertical scaling increases RC charging times. lateral scaling should decrease RC charging times. HBT bandwidths should then increase. But, HBTs must first be modified . . . Scaling for THz device bandwidths Current-gain cutoff frequency in HBTs kT 1 kT base collector C je Cbc Rex Rcoll 2f qIE qIE base Tb2 2Dn collector Tc 2vsat Collector velocities can be high: velocity overshoot in InGaAs Base bandgap grading reduces transit time substantially RC terms quite important for > 200 GHz ft devices Excess Collector-Base Capacitance in Mesa HBTs • base contacts: must be > 1 transfer length (0.3 mm) sets minimum collector width sets minimum collector capacitance Ccb • base resistance spreading resistance scales with emitter scaling contact resistance independent of emitter scaling sets minimum base resistance sets minimum RbbCcb time constant fmax does not improve with submicron scaling Transferred-Substrate HBTs: A Scalable HBT Technology 1000 f max , GHz 800 600 0.5 mm base Ohmics 400 1.0 mm base Ohmics 200 0 0 0.5 1 emitter w idth, microns • Collector capacitance reduces with scaling: Ccb We • Bandwidth increases rapidly with scaling: f max 1 We 1.5 Thinning base, collector epitaxial layers improves ft, degrades fmax Lateral scaling provides moderate improvements in fmax Regrowth (similar to Si BJT !) should help considerably Transferred-substrate helps dramatically Undercut-Collector Device for high fmax emitter base contact undercut collector junction InGaAs collector InGaAs base InP collector InGaAs subcollector InP subcollector SI substrate Lucent Technologies (YK Chen) TRW Texas Instruments collector contact Integrated Circuit Technology transistor resistor capacitor microstrip bypass capacitor C B E BCB gold thermal via ground via gold ground plane In/Pb/Ag solder GaAs carrier wafer metal 1 polyimide metal 2 SiN NiCr contact • very high HBT bandwidths, low interconnect capacitance, low ground-return inductance, low thermal resistance 50 mm transferred-substrate HBT Wafer: Cu substrate AlInAs/GaInAs graded base HBT 0.5 Emitter Collector depletion region 0 -0.5 -1 Schottky collector Graded base -1.5 -2 0 1000 2000 3000 4000 Distance, Å 5000 6000 Band diagram under normal operating voltages V ce = 0.9 V, V be= 0.7 V • 400 Å 5E19 graded base ( DEg = 2kT), 3000 Å collector Transferred-Substrate Heterojunction Bipolar Transistor Device with 0.6 µm emitter & 1.8 µm collector extrapolated fmax at instrument limits, >400 GHz 35 Mason's Gain, U 30 Gains, dB 25 20 H 15 f 21 max 10 5 f =215 GHz 0 1 10 100 Frequency, GHz =470 GHz Why Mason’s Gain, U, is used to find fmax: 40 40 30 Gains, dB MAG/MSG can be above U ...above -20 dB/dec line U MA G/MSG 25 20 15 10 U 30 MA G/MSG 25 20 15 10 (CE, small Ccbx ) 5 ( CE, large Ccbx ) 5 0 0 1 10 Frequency, GHz 100 40 U: all 3 35 30 Gains, dB MAG/MSG can be below U …below -20 dB/dec line 35 Gains, dB 35 25 U is same for CE , CB, & CC MA G/MSG common emitter 20 15 MA G/MSG common base 10 5 MA G/MSG common collector 10 Frequency, GHz 100 U is not changed by pad parasitics U has -20 dB / decade slope to fmax MSG slope is -10 dB / decade MAG has no fixed slope -for hybrid- model comment: U is not given by: 0 1 1 10 Frequency, GHz 100 S 21 2 1 S 1 S 2 11 Plots generated using HP / EESOF simulator and standard hybrid- model 2 22 Measuring High fmax Transistors I DC-50 GHz & 75-110 GHz Network Analysis waveguide-coupled micro-coax probes Parasitic probe-probe coupling S12 error background: not corrected by calibration gain measurements corrupted, worse for W-band corrupted W-band measurement Measuring High fmax Transistors II Offset reference planes, on-wafer LRL calibration standards separate probes to reduce coupling reference planes at transistor terminals 230 mm 230 mm Line-reflect-line on-wafer cal. standards Lo+1275 mm+Lo 20-60 GHz LINE Lo+560 mm+Lo 75-110 GHz LINE Lo+Lo 20-60 GHz Calibration standards THROUGH LINE SHORT Lo Lo 75-110 GHz Calibration standards Calibration verification OPEN (reflect) DUT Lo Lo Lo Lo V= 2.04 x 108 m/s (er = 2.7) Device under test Submicron Transferred-Substrate HBT 30 Mason's gain, U Gains, dB 25 20 MSG 15 H 10 emitter, 0.4 x 6 mm 2 5 21 f = 204 GHz collector, 0.4 x 6 mm I = 6 mA, V = 1.2 V 2 c f max = 1.1 THz ce 0 10 100 Frequency, GHz 20 dB / decade gain slope may NOT continue to 1 THz 1000 Bandwidth vs Current Density Bandwidth vs Vce Decrease in f decreasing electron velocity with increased field Ccb Cancellation by Collector Space-Charge Vcb collector space-charge layer Qbase eA I cTc Vcb Tc Vcb 2vsat c eA Ccb Ic Tc Vcb Collector space charge partially screens collector field. Increasing voltage decreases electron velocity, modulates collector space-charge offsets modulation of base charge Ccb is reduced Moll & Camnitz 1992, Betser & Ritter 1999, Englemann & Liechti 1977 (MESFETs) Measured Variation of Collector Transit Time with Bias f data predicts 0.9 fF capacitance cancellation, 1 vs 6 mA Capacitance cancellation: measured measured 0.64 fF decrease, 16 mA (vs 0.9 fF predicted) Expected Ccb reduction is observed in microwave Y12 Device Model S 21 /5 10 x S 12 Element parameters are physically reasonable S S 22 11 measured equivalent circuit Emitter Profile: Stepper Device 0.5 mm emitter stripe 0.15 mm e/b junction Transferred-Substrate HBT: Stepper Lithography 30 Gains, dB 25 Mason's gain, U 20 15 10 H 21 f = 147 GHz f max = 805 GHz 5 0 100 Frequency, GHz 0.4 mm emitter, ~0.7 mm collector 1000 DC characteristics, stepper device We=0.2 X 6 mm2 Wc=1.5 X 9 mm2 b=50 Given high fmax, vertical scaling exhanges reduced fmax for increased f Transit times: HBT with 2kT base grading 1.2 0.8 b c 0.41 ps RexCcb 0.114 ps 1/2f (ps) 1 0.6 C je g m 0.065 ps 0.51 ps 0.4 Ccb g m 0.045 ps f 252GHz 0.2 total 0.634 ps 0 0 0.1 0.2 0.3 0.4 1/I (1/mA) c 2000 Å InGaAs collector 400 Å InGaAs base, 2kT bandgap grading 0.5 0.6 Gains: HBT with 2kA collector, 300 A base 40 H 35 21 Gains (dB) 30 25 20 Mason's Gain, U 15 f =275 GHz 10 f 5 =245 GHz max 0 1 10 Frequency (GHz) 100 Why would you want a 1 THz transistor ? Digital microwave / RF transmitters (DC-20 GHz) direct digital synthesis at microwave bandwidths microwave digital-analog converters Digital microwave / RF receivers delta-sigma ADCs with 10-30 GHz sample rates 16 effective bits at 100 MHz signal bandwidth ? Basic Science: 0.1 µm Ebeam device: 1000 GHz transistor (?) transistor electronics in the far-infrared Fast fiber optics, fast digital communications: 200 GHz f, 500 GHz fmax device: ~ 75-90 Gb/s 160 Gb/s needs ~350 GHz f, 500 GHz fmax Transferred-Substrate HBT ICs: Key Features 100 GHz clock-rate ICs will need: very fast transistors short wires –> high IC density –> high thermal conductivity low capacitance wiring low ground inductance –> microstrip wiring environment Transferred Substrate HBT ICs offer: 800 GHz fmax now , > 1000 GHz with further scaling 250 GHz ft now, >300 GHz with improved emitter Ohmics copper substrates / thermal vias for heatsinking low capacitance (e= 2.5) wiring THz-Bandwidth HBTs ??? deep submicron transferred-substrate regrown-base HBT 4 5 2 1 3 1) regrown P+++ InGaAs extrinsic base --> ultra-low-resistance 2) 0.05 µm wide emitter --> ultra low base spreading resistance 3) 0.05 µm wide collector --> ultra low collector capacitance 4) 100 Å, carbon-doped graded base --> 0.05 ps transit time 5) 1kÅ thick InP collector --> 0.1 ps transit time. Projected Performance: Transistor with 500 GHz ft, 1500 GHz fmax The wiring environment for 100 GHz logic Why is Improved Wiring Essential? ground return loops create inductance Wire bond creates ground bounce between IC & package 30 GHz M/S D-FF in UCSB - mesa HBT technology Ground loops & wire bonds: degrade circuit & packaged IC performance Ground Bound Noise in ADCs ADC digital sections input buffer Lground ground bounce noise D Vin ground return currents Ground bounce noise must be ~100 dB below full-scale input Differential input will partly suppress ground noise coupling ~ 30 to 40 dB common-mode rejection feasible CMRR insufficient to obtain 100 dB SNR Eliminate ground bounce noise by good IC grounding Microstrip IC wiring to Eliminate Ground Bounce Noise Brass carrier and assembly ground IC with backside ground plane & vias interconnect substrate near-zero ground-ground inductance IC vias eliminate on-wafer ground loops Transferred-substrate HBT process provides vias & ground plane. Power Density in 100 GHz logic Transistors tightly packed to minimize delays 105 W/cm2 HBT junction power density. ~103 W/cm2 power density on-chip 75 C temperature rise in 500 mm substrate. Solutions: Thin substrate to < 100 mm Replace semiconductor with metal copper substrate Transferred-Substrate HBT Integrated Circuits 11 dB, 50+ GHz AGC / limiting amplifier 47 GHz master-slave flip-flop 10 dB, 50+ GHz feedback amplifier 7 dB, 5-80 GHz distributed amplifier Transferred-Substrate HBT Integrated Circuits multiplexer 2:1 demultiplexer (120 HBTs) 16 dB, DC-60 GHz amplifier 6.7 dB, DC-85 GHz amplifier W-band VCO Clock recovery PLL 6.7 dB, 85 GHz Mirror Darlington Amplifier 8 21 Forward Gain, S , dB 10 6 4 2 0 0 20 40 60 Frequency, GHz 80 • 6.7 dB DC gain • 3 dB bandwidth of 85 GHz • f-doubler (mirror Darlington) configuration 100 18 dB, DC to > 50 GHz Darlington Amplifier 20 S21 15 10 5 0 S11 -5 -10 S22 -15 -20 0 10 20 30 40 50 Frequency (GHz) Over 400 GHz Gain-BW, 2 transistors Master-Slave Flip Flop: 100 GHz design target master, slave, clock buffer, output buffer: 76 HBTs 33.0 GHz static divider output at 66.0 GHz input Measurement is setup-limited (source, bias tee, probe) Fiber Optic ICs PIN / transimpedance amplifier (not yet working !) AGC / limiting amplifier CML decision circuit Delta-Sigma ADC In Development (300 HBTs) Transferred Substrate HBTs An ultrafast bipolar integrated circuit technology Ultrahigh fmax HBTs Low capacitance interconnects Superior heat sinking, low parasitic packaging Demonstrated: HBTs with 1 THz extrapolated fmax >66 GHz flip-flops, 85 GHz amplifiers, ... Future: 0.1 mm HBTs with fmax >> 1000 GHz (0.1 mm, carbon) 100 GHz digital logic ICs --> DACs, DDS, ADCs, fiber