Transcript The ARM Programmer’s Model Jacob Huerta, Ryan Crell, and Veronica Hohe 1/30/2015 Outline         ARM Registers Von Neumann Cycle Sequence CPSR Memory Standard ARM vs.

The ARM Programmer’s
Model
Jacob Huerta, Ryan Crell, and Veronica Hohe
1/30/2015
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Outline
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ARM Registers
Von Neumann Cycle Sequence
CPSR
Memory
Standard ARM vs. Thumb ARM Instructions
ARM Instructions
Supervisor Mode/Kernel Mode
Exceptions
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ARM Registers
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ARM Registers
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Instruction set =
operations to change
system state
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State = data items in
processor’s visible
registers/systems memory
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Multiple invisible
registers in a processor
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ARM Registers
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User-level programming
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15 general purpose
registers
PC
CPSR
System-level
programming/exceptions
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Remaining registers
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Von Neumann Cycle Sequence
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Von Neumann Cycle Sequence
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CPSR
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ARM CPSR Control Bits
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Protected from user-level programs
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Mode
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T
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Control the instruction set
State bit
IF
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Control the processor mode
Bits 0-4 (must be a valid mode)
Enables control interrupt
Bit 6 is FIQ disable and Bit 7 is IRQ disable
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ARM CPSR Flag Bits
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Condition Code Flags NZCV
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N (“Negative flag”)
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Z (“Zero flag”)
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0/1 = “extends” for shift/”borrows” for subtraction
V (“Overflow flag”)
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0/1 = result is non-zero/zero
C (“Carry flag”)
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0/1 = value is positive/negative
0/1 = no overflow/overflow caused by last arithmetic operation
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ARM CPSR Unused Bits
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Unused bits
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Reserved
State preserved when changing the flag or control bits
Should not be altered by programs
Should not rely on them when checking the PSR status
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Might read as 1’s or 0’s in future processors
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ARM Memory Organization
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ARM Memory Organization
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View memory as linear array of
bytes numbered from 0 to 232-1
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Store data items in
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Byte (8 bits)
Half-word (16 bits)
Word (32 bits)
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Align words on 4 bytes
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Organize in little-endian style
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ARM Instructions
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ARM vs. THUMB Instructions
ARM
 32-bit instruction set
 3-data address instructions
 16 general purpose
registers
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THUMB
 16-bit instruction set
 2-data address instructions
 8 general purpose registers
 “Less regular” instructions
 Higher code density
 High performance
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ARM vs. THUMB Instructions
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Not a “complete” architecture
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Supports ARM architecture
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The T bit in CPSR toggles the interpretation
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ARM vs. THUMB Instructions
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ARM Instructions
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Load-store architecture
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Processes only values stored in registers and instructions
Performs operations on these values
Stores results in register
Affects memory using only load and store instructions
Inability to perform memory-to-memory operations
Instructions
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Data processing: between registers (add, sub, etc.)
Data transfer: between registers and memory (load, store)
Control flow: execution of instructions (branches, link, supervisor
calls)
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Supervisor Mode/Kernel Mode
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Supervisor Mode/Kernel Mode
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User with supervisor privileges can use system calls to affect
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Kernel code
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Device drivers
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Privileged code
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Unprivileged code
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User program with IO
access permissions
User programs
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Exceptions
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Exceptions
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Normal execution is paused to handle events like
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Systems calls
Interrupts generated by external sources
Undefined instructions
Traps
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Exception Handling
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Save current state is
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Copy PC into register rl4_exc
Copy CPSR into register SPSR_exc
Register r13_exc = pointer to memory stack to store user
registers
Set processor operating mode to exception mode
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Exception Handling
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Set PC to value between 0x00 and 0x1C depending on
exception type
Restore user registers from memory stack
Restore (adjusted) PC and CPSR
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Input/Output (I/O) System
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Input/Output (I/O) System
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I/O peripheral
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Device mapped to memory
Device registers treated as memory locations by system
Given interrupt support (make interrupt requests)
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Normal interrupt (IRQ) = most requests
Fast interrupt (FIQ) = time-sensitive/critical requests
Direct Memory Access (DMA)
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External to ARM processor
Handles high-bandwidth I/O traffic
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References
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(2001). “The Thumb Instruction Set.” Web. 2001. January 28, 2015.
http://paulkilloran.com/arm/Lecture_7.pdf
(2014). “About processor exceptions.” ARM. Web.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html.
(2014). “Exception handling process.” ARM. Web.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html.
(2014). “Load/store architecture.” Wikipedia. Web. August 4, 2014.
http://en.wikipedia.org/wiki/Load/store_architecture.
(2014). “Protection ring.” Wikipedia. Web. December 30, 2014.
http://en.wikipedia.org/wiki/Protection_ring.
(2014). “Reserved bits.” ARM. Web. August 4, 2014.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0229c/ch02s07s03.html
(2014). “Trap (computing).” Wikipedia. Web. April 30, 2014.
http://en.wikipedia.org/wiki/Trap_(computing).
Furber, S. (2000). ARM system-on-chip architecture. Harlow, England: Addison-Wesley. (2014).
Gibson, J. (2011). ARM assembly language: An Introduction (2nd ed.). Lexington, KY: The Author.
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QUESTIONS?
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