Transcript Chapter 5

Chapter 5
Introduction To The ARM
Microprocessor
(Real-Time Embedded Multithreading : Using ThreadX® and ARM®)
Department of Computer Science Hsu Hao Chen
Professor Hsung-Pin Chang
Outline
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ARM Features
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ARM Architecture
SoC、Reduced Power Consumption
Improved Code Density
Versatile Register Set
CPSR Definition
Processor Modes
ARM Power Saving Support
ARM Architecture(1/2)
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Load-Store Architecture- Moving data in memory
to and from the register set can reduces the
complexity of the instruction addressing operands.
Fixed Length Instructions- This eliminates the
need to calculate the instruction size and the
potential for multiple memory accesses to complete a
single instruction fetch.
Orthogonal Registers- Most ARM registers can be
used for address or data(37 32-bits registers)
Single Cycle Execution- Most ARM instructions
execute in a single processor cycle except for the
load and store instructions.
ARM Architecture(2/2)
Soc、Reduced Power Consumption(1/2)
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Soc
Soc、Reduced Power Consumption(2/2)
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Reduced Power Consumption
Normal mode
Low Power mode
Improved Code Density (1/2)
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Code density is measured how much work a
processor can perform versus program size.
One common problem with RISC architecture
is low code density.
Cause and Effect of RISC instructions:
RISC instructions are so simple and required
to perform the same higher-level function
that this would result in a lower code density.
Improved Code Density (2/2)
Solutions of low code density as follows:
 Thumb:
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Processor recognizes a fixed-length 16-bit
instruction set and the 32-bit ARM instruction set.
A program compiled for Thumb is smaller than the
compiled version for a CISC machine.
Conditional instruction execution:
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eliminated the branch
preserved the instruction pipeline
Versatile Register Set(1/2)
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The ARM architecture has a total of 37 32 bits registers.
Following figure 5.1, ARM 32-bit mode is compared with Thumb state
register sets:
Versatile Register Set(2/2)
Where are User Program Mode and System Mode ？
CPSR Definition(1/2)
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The CPSR defines the mode (physical
registers being used).
Interrupts are enable or disable.
32 bit or 16bit (Thumb) instructions are
currently being executed.
CPSR Definition(2/2)
Processor Modes
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User Program Mode:
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The mode is not allowed access to system
registers.
Typically used by larger operating systems when
executing application level programs
Processor Modes
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Fast Interrupt (FIQ) Mode:
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The mode typically is reserved for processing
high-frequency or low-frequency interrupts
Because registers r8_fiq through r12_fiq can
be used without saving and restoring context
Normal Interrupt (IRQ) Mode
Processor Modes
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Supervisor (SVC) Mode:
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This is another typical program execution
mode.
Most embedded systems execute their
programs in this mode.
Abort Mode:
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This program exception mode is used for
handling instruction fetch abort and data
memory access abort condition.
Processor Modes
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Undefined Mode:
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This program exception mode is used for handling
undefined instruction error conditions.
System Mode:
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This is another typical program execution mode that
was first available to the version 4 architectures of
ARM.
This is another viable execution mode for typical
embedded system programs.
Processor Modes
version 3 architectures of ARM
ARM Power Saving Support (1/2)
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When processors are sleeping, ARM
processors enable to enter low power
mode and will stay until interrupt mode
(debug event) occurs.
The only difficulty of entering low
power mode is determining if any
periodic events are currently scheduled.
ARM Power Saving Support (2/2)
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Solutions for entering low power mode:
tx_timer_get_next:
a. returned the next expiration time
b. called before entering low power mode
c. the value returned should be used to
reprogram the ThreadX timer to expire at the
appropriate time.
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tx_time_increment:
used when the processor awakes to adjust
the internal ThreadX timer to the number of
timer-ticks.
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