Transcript 2010 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 2010, Montreal 100+ GHz Transistor Electronics: Present and Projected Capabilities Mark Rodwell University of.

2010 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 2010, Montreal
100+ GHz Transistor Electronics:
Present and Projected Capabilities
Mark Rodwell
University of California, Santa Barbara
[email protected] 805-893-3244, 805-893-5705 fax
THz Transistors
Why Build THz Transistors ?
500 GHz digital logic
→ fiber optics
THz amplifiers→ THz radios
→ imaging, sensing,
communications
precision analog design
at microwave frequencies
→ high-performance receivers
Higher-Resolution
Microwave ADCs, DACs,
DDSs
Transistor figures of Merit / Cutoff Frequencies
gains, dB
H21=short-circuit current gain
MAG = maximum available
power gain:
impedance-matched
fmax
power-gain
cutoff frequency
ft
current-gain
cutoff frequency
U= unilateral power gain:
feedback nulled,
impedance-matched
What Determines Digital Gate Delay ?
f
CV/I terms
 0 . 5t f I C /  V L ) dominate
 (  V L / I C )( C je  6 C cbx  6 C cbi  C wire )
 ( kT / qI C )( 0 . 5 C je  C cbx  C cbi
→
T gate  t
 R ex ( 0 . 5 C cbx  0 . 5 C cbi  0 . 5t f I C /  V L )
 R bb ( 0 . 5 C je  C cbi  0 . 5t f I C /  V L ).
analog ICs have somewhat similar bandwidth considerations...
How to Make
THz Transistors
High-Speed Transistor Design
Depletion Layers
C 
Fringing Capacitances
A
T
t 
C finging / L ~ 
T
C finging / L ~ 
2v
I max

A
4  v sat (V appl   )
T
Thermal Resistance
2
Bulk and Contact Resistances
R th 
R   contact / A
contact te
rms dominate
1
 L 
ln 

 K th L  W   K th L
1
Frequency Limits
and Scaling Laws
of (most)
Electron Devices
PIN photodiode
R top
t  thickness
C  area / thickness
R top   contact / area
R bottom 
I max,
 contact
area
T 
length
 sheet
4
space - charge - limit
power

R bottom
 area /

width
length
 thickness 
2
 length 
 log 

 width 
To double bandwidth,
reduce thicknesses 2:1
Improve contacts 4:1
reduce width 4:1, keep constant length
increase current density 4:1
Changes required to double transistor bandwidth
We
emitter
length
LE 
HBT parameter
emitter & collector junction widths
current density (mA/mm2)
current density (mA/mm)
collector depletion thickness
base thickness
emitter & base contact resistivities
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
nearly constant junction temperature → linewidths vary as (1 / bandwidth)2
LG
gate
width W G 
constant voltage, constant velocity scaling
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
change
decrease 2:1
increase 2:1
increase 2:1
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
Electron Plasma Resonance: Not a Dominant Limit
T
L kinetic 
R bulk 
dielectric
relaxation
f dielectric 

n - InGaAs
3 . 5  10
19
/ cm
frequency
1 / 2
C displaceme
1 
2 
nt
R bulk
1
2
A q nm
T
7  10
/ cm
3
nt

T
1
A q nm t m
2
*
scattering
frequency
f scattering 

1
R bulk
2  L kinetic
plasma
frequency
f plasma 
1 / 2
L kinetic C displaceme
1
2 t m
800 THz
7 THz
74 THz
80 THz
12 THz
3 1 THz
3
p - InGaAs
19
C displaceme
*
A
nt
Thermal Resistance Scaling : Transistor, Substrate, Package
cylindrica
spherical
l heat flow
 L
ln  e
 K InP L E  W e
P

P

 K
InP

increases
 T package
jun ctio n te m p e ra tu re ris e , K e lv in
140
cally
for r  D HBT / 2
 1
1 
P  T sub  D / 2 





2
L
 K
D
D


InP
 E

insignific
logarithmi
planar flow
for r  L e
near junction
 T substrate 
flow
increases
ant
quadratica
lly
if T sub is constant
variation
 1 1  Pchip
  
 4   K Cu W chip
T sub  40 m m  (150 GHz / f clock )
120
Wiring
to tal
lenghts
2000 - HBT CML IC
scale as
100
80
1/bandwidt
su b s tra te : c ylin d rica l+ s p h e rica l re g io n s
60
Power density,
package
40
scales as
s u b s tra te : p la n a r re g io n
20
(bandwidth
0
100
200
300
400
h.
500
600
m a ste r-sla ve D -F lip-F lo p clo ck fre qu e n cy, G H z
700
2
) .
Thermal Resistance Scaling : Transistor, Substrate, Package
cylindrica
spherical
l heat flow
 L
ln  e
 K InP L E  W e
P

P

 K
InP

increases
 T package
jun ctio n te m p e ra tu re ris e , K e lv in
140
cally
for r  D HBT / 2
 1
1 
P  T sub  D / 2 





2
L
 K
D
D


InP
 E

insignific
logarithmi
planar flow
for r  L e
near junction
 T substrate 
flow
increases
ant
quadratica
lly
if T sub is constant
variation
 1 1  Pchip
  
 4   K Cu W chip
T sub  40 m m  (150 GHz / f clock )
120
Wiring
lenghts
Probable best solution:
scale as
1/bandwidt h.
Thermal Vias ~500 nm below InP subcollector
Power density,
...over full active IC area.
scales as
to tal
2000 - HBT CML IC
100
80
su b s tra te : c ylin d rica l+ s p h e rica l re g io n s
60
package
40
s u b s tra te : p la n a r re g io n
20
(bandwidth
0
100
200
300
400
500
600
m a ste r-sla ve D -F lip-F lo p clo ck fre qu e n cy, G H z
700
2
) .
Bipolar
Transistors
150 nm thick collector
256 nm InP HBT
40
340 GHz
dynamic
frequency
divider
Z. Griffith
10
2
30
21
20
f
10
M. Seo, UCSB/TSC
U
m ax
8
m A /m m
dB
H
6
4
= 780 G Hz
2
f = 424 G H z
10
10
10
9
10
Hz
70 nm thick collector
M. Seo, UCSB/TSC
IMS 2010
11
10
0
12
H
m ax
4
5
ce
20
2
E. Lind
m A /m m
dB
f
3
21
U
20
Vout
2
V
30
VBB
VEE
1
12
10
10
10
0
11
Vtune
t
10
340 GHz VCO
0
9
10
= 560 G H z
15
10
10
324 GHz
amplifier
5
f = 560 G Hz
t
0
0
J. Hacker, TSC
IMS 2010
10
9
10
10
10
11
10
0
12
1
2
V
Hz
3
4
ce
40
30
H
Z. Griffith, TSC
CSIC 2010:
to be presented
U
m A /m m
Z. Griffith
2
30
dB
204 GHz
static
frequency
divider
21
20
10
f
m ax
= 218 G H z
20
10
f = 660 G H z
0
9
10
t
much better results in press ...
10
10
10
Hz
11
10
12
0
0
1
2
V
ce
3
InP Bipolar Transistor Scaling Roadmap
emitter 512
16
256
8
128
4
64
2
32 nm width
1 mm2 access 
base
300
20
175
10
120
5
60
2.5
30 nm contact width,
1.25 mm2 contact 
collector 150
4.5
4.9
106
9
4
75
18
3.3
53
36
2.75
37.5 nm thick,
72 mA/mm2 current density
2-2.5 V, breakdown
520
850
430
240
730
1300
660
330
1000
2000
1000
480
1400 GHz
2800 GHz
1400 GHz
660 GHz
ft
fmax
power amplifiers
digital 2:1 divider
370
490
245
150
We
Tb
W bc
Tc
Fabrication Process for 128 nm & 64 nm InP HBTs
Chart 17
Initial Results: Refractory-Contact HBT Process
30
110 nm emitter width
30
U
270 nm emitter width
U
25
25
20
H
f
21
m ax
= 700 G H z
G a in (d B )
G a in (d B )
H
15
A
10
je
= 0 .1 1 m m x 3 .5 m m
21
20
f
15
A
je
m ax
= 800 G H z
= 0 .2 7 m m x 3 .5 m m
10
f = 370 G H z
t
5
5
f = 430 G H z
t
0
10
9
10
10
10
F re q (H z)
11
10
12
0
9
10
10
10
10
11
fre q (H z)
Need to add E-beam defined base, best base contact technology
10
12
InP DHBTs: August 2010
4 00
GHz
1000
5 00
GHz
6 00
GHz
7 00
GHz
8 00
GHz
9 00
G Hz

popular
f t f m ax
T e le d yn e D H B T ( f t  f max ) / 2
U IU C D H B T
800
f
max
(G H z )
NTT DBHT
250 nm
600
(1 f t  1 f max )
1
much better metrics
U IU C S H B T
250 nm
600nm
200
PAE, associated
NGST DHBT
mW/ m m
IB M S iG e
350 nm
power amplifiers
UCSB DHBT
H RL D HB T
Fmin , associated
f clock , hence
( C cb  V / I c ),
U p da te d A u g 20 1 0
0
400
600
f (G H z)
t
800
1000
:
low noise amplifiers
digital :
V ite sse D H B T
200
f t f max
ETHZ D HBT
110 nm
0
:
f t or f max alone
200 nm
400
metrics
( R ex I c /  V ),
( R bb I c /  V ),
(τb  τc )
gain,
:
gain,
:
670 GHz Transceiver Simulations in 128 nm InP HBT
transmitter exciter
Simulations @ 670 GHz (128 nm HBT)
LNA: 9.5 dB Fmin at 670 GHz
30
PA: 9.1 dBm Pout at 670 GHz
35
35
20
20
30
30
10
0
receiver
660
680
S P .fre q , G H z
fre q , G H z
700
720
800
820
G a in
Pout
0
-8860 -6
-4880 -2
(b )
0
0 900 2
128nm
4 0.986
(c )
free-running
VCO
0
Total PLL
phase noise
-50
closed-loop
VCO noise
-100
multiplied
reference noise
-150
1
10
2
3
4
10
6
10
7
950 GHz Input
-0.9
-0.95
-0.95
Vout, Vout_bar
Vout , Vout_bar
5
10
10
10
offset from carrier, Hz
690 GHz Input
-1
-1.05
-1.1
-1.15
-1
-1.05
-1.1
-1.15
197.5 10
-12
200 10
-1.2
-12
195 10
-12
Noise Figure, Conversion Gain (dB)
197.5 10
-12
time, seconds
time, seconds
Mixer:
10.4 dB noise figure
11.9 dB gain
-8
50
-0.9
-1.2
-12
195 10
1.04
-1 0
S P .fre q , TH z
fre q , TH z
(a)
10
Dynamic divider:
novel design,
simulates to 950 GHz
3
-1 0
1.02 -1 2
8 1.001 0
P in
S P .fre q , G H z
fre q , G H z
VCO:
-50 dBc (1 Hz)
@ 100 Hz offset
at 620 GHz (phase 1)
3-layer thin-film THz interconnects
thick-substrate--> high-Q TMIC
thin -> high-density digital
5
-5
6 4 nm
-1 0
840 -1 0
(a )
10
20
10
0
1 2 8 nm
640
5
-5
0
620
n f(2 )
d B (S (2 ,1 ))
10
15
10
20
PLL single-sideband
phase noise spectral density, dBc (1 Hz)
20
G a in
Pout
n f(2 )
d B (S (2 ,1 ))
n f(2 )
d B (S (2 ,1 ))
15
30
25
20
15
10
5
0
-5
-15.00
-10.00
-5.000
0.0000 5.000
LO Power
10.00
200 10
-12
1.-
THz
Field-Effect Transistors
(THz HEMTs)
FET Scaling Laws
LG
Changes required to double device / circuit bandwidth.
laws in constant-voltage limit:
gate
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
electron mass in transport direction
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
change
decrease 2:1
increase 2:1
increase 2:1
constant
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
width W G 
HEMT/MOSFET Scaling: Four Major Challenges
contact regions:
need reduced
access resistivity
channel:
need higher charge density
yet keep high carrier velocity
gate dielectric:
need thinner barriers
→ tunneling leakage
channel:
need thinner layers
THz FET Scaling Roadmap
Gate length
Gate barrier EOT
well thickness
S/D resistance
effective mass
# band minima
ft
fmax
fdivider source-coupled logic
Id /Wg@ 200 mV overdrive
nm
nm
nm
1
25
0.58
4.0
100
0.05
1
18
0.41
2.8
74
0.08
2
GHz
700
770
GHz
GHz
810
150
mA/mm 0.54
mm
*m0
high-K gate dielectrics
35
0.83
5.7
150
0.05
?
13
2.0
53
9
0.21
1.4
37
0.08
3
0.08
3
1100
1600
2300
930
220
1400
300
2000
430
2900
580
0.69
0.95
1.4
1.8
0.29
source / drain regrowth
G-L transport
III-V MOSFETs with Source/Drain Regrowth
27 nm InGaAs MOSFET
Regarding
Mixed-Signal ICs
&
Waveform Generation
Clock Timing Jitter in ADCs and DACs
Timing jitter is quantitatively specified
by the single-sideband phase noise spectral density L(f).
IC oscillator phase noise varies as ~1/f2 or ~1/f3 near carrier
Impact on ADCs and DACs:
imposition of 1/fn sidebands on signal of relative amplitude L(f)
...not creation of a broadband noise floor.
Dynamic range of electronic DACs & ADCs is limited by factors
other than the phase noise of the sampling clock
Why ADC Resolution Decreases With Sample Rate
Dynamic Range Determined by Circuit Settling Time vs. Clock Period
dynamic hysteresis
metastability
# bits 
1
f sample t latch
IC time constants→ Resolution decreases at high sample rates
Fast IC Waveform Generation: General Prospects
Waveform generator → fast digital memory & DAC
Parallel digital memory and 200 Gb/s MUX is feasible
cost limits: power & system complexity vs. # bits, GS/s
Performance limit: speed vs. resolution of DAC
faster technologies → increased sample rates
Feasible ADC resolution:
12 SNR bits @ 4 GS/s feasible using 500 nm (400GHz) InP HBT.
Feasible sample rate will scale with technology speed..
THz Transistors
&
Mixed-Signal ICs
Few-THz Transistors
Few-THz InP Bipolar Transistors: can it be done ?
Scaling limits: contact resistivities, device and IC thermal resistances.
62 nm (1 THz ft , 1.5 THz fmax ) scaling generation is feasible.
700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation feasible ?
Few-THz InP Field-Effect Transistors: can it be done?
challenges are gate barrier, vertical scaling,
source/drain access resistance, channel density of states.
2DEG carrier concentrations must increase.
S/D regrowth offers a path to lower access resistance.
Solutions needed for gate barrier: possibly high-k (MOSFET)
Implications: 1 THz radio ICs, ~200-400 GHz digital ICs, 20 GHz ADCs/DACs