Transcript Loop Gain (Aolb) - TI E2E Community

Solving Op Amp Stability Issues
(For Voltage Feedback Op Amps)
Tim Green & Collin Wells
Precision Analog Linear Applications
1
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Overview
Main Presentation Focus:
1) Op Amp Stability Basics
2) Stability Analysis – Method 1 : Loaded Aol & 1/b Technique
A) Riso Compensation Technique for Output Capacitive Loads
3) Stability Analysis – Method 2 : Aol & 1/b Technique
A) CF Compensation Technique for Input Capacitance
4) Stability Tricks and Rules of Thumb
Appendix:
1) Additional Useful Tools for your Analog Stability Toolbox
A) Op Amp Output Impedance
B) Pole and Zero: Magnitude and Phase on Bode Plots
C) Dual Feedback Paths and 1/b
D) Non-Loop Stability Problems
2) Nine different ways to stabilize op amps with capacitive loads
A) Definition by example using TINA-TI simulations
4
The Culprits
Output Capacitive Loads!
Cable/Shield Drive!
Reference Buffers!
Rg 1k
MOSFET Gate Drive!
Q1
Rf 20k
+
VReg
OPA
U1 REF5025
-
Vin
+
VIN 5
Cin 1u
Vout
Tem p
Vin
-
OPA
Shielded Cable
ADC_VREF
C_Cable 10n
R1 20k
Vout
+
C3 10u
RL 250
C4 100n
Vin 10
OPA
RL 200
-
VREF
C1 1u
GND Trim
-
VREF 2.5
C2 1u
+
OPA
R2 20k
VRef 2.5
+
Input Capacitance and Large Value Resistors
Large Value Resistors or
Low-Power Circuits!
Transimpedance Amplifiers!
R4 499k
Rf 1M
R3 499k
IOP2
-
OPA
+
D1
Vin
TVS
Rf 49k
D2
Vo
Id
Rg 4.99M
+
VG2
Rd 4.99G Cd 10p
V+
+
Photodiode
Model
Transient Suppression!
-
Vout
Cin 25p
+
Cd 200p
OPA
Vout
+
5
Just Plain Trouble!
Inverting Input Filter??
Oscillator
10.00m
Rg 10k
Rf 100k
VG1
+
0.00
62.12m
Vin
Cin 1u
-
Vfb
OPA
-37.08m
1.16
Vout
+
Vo
-1.00
1.95m
Output Filter??
2.23m
Time (s)
2.50m
Oscillator
10.00m
VG1
R1 10k
-
0.00
62.12m
OPA
Vfb
V1 5
Vout
-37.08m
1.16
+
R2 49k
C1 10u
C5 100n
Vo
-1.00
1.95m
2.23m
Time (s)
2.50m
6
Transient on:
+Input or –Input
Vcc or Vee
Output
4
2
Vcc
-
R1 49kOhm
1
3
+
+
5
But it worked fine
in the lab!
VOUT
+2.5V
U1 OPA333
VIN
Vcc
+2.5V
C1
100nF
Vcc 5V
CLoad 1uF
R2 49kOhm
But I’m only
using it at DC!
3.0
Check ALL Op
Amp Circuits for
Stability
regardless of
their closed loop
signal frequency
of operation!
2.5
VOUT
2.0
7
1.5
0
500u
1m
Time (s)
2m
2m
Recognize Amplifier Stability Issues on the Bench
• Required Tools:
– Oscilloscope
– Signal Generator
• Other Useful Tools:
– Gain / Phase Analyzer
– Network / Spectrum Analyzer
8
Recognize Amplifier Stability Issues
• Oscilloscope - Transient Domain Analysis:
Oscillations or Ringing
Overshoots
Unstable DC Voltages
High Distortion
18.53m
Voltage (V)
–
–
–
–
0.00
1.75m
2.75m
21.88m
Voltage (V)
15.00
Output
2.25m
Time (s)
0.00
-14.83
1.75m
50.88m
Time (s)
100.00m
0.00
1.75m
2.25m
Time (s)
2.75m
9
Recognize Amplifier Stability Issues
• Gain / Phase Analyzer - Frequency Domain:
- Peaking, Unexpected Gains, Rapid Phase Shifts
40.00
Gain (dB)
20.00
0.00
-20.00
-40.00
-60.00
Phase [deg]
0.00
-180.00
-360.00
1.00
10.00
100.00
1.00k
10.00k
Frequency (Hz)
100.00k
1.00M
10.00M
100.00M
10
Quick Op-Amp Theory
Bode Plot Review
Basic Stability Tools
11
Poles and Bode Plots
G
R
fP
100
Straight-Line Approximation
80
VIN
-20dB/Decade
-6dB/Octave
C
60
fp 
40
1
2RC
Single Pole Circuit Equivalent
20
 Pole Location = fP
0
1
10
100
1k
10k
100k
1M
10M
 Magnitude = -20dB/Decade Slope
Frequency (Hz)
+90

Slope begins at fP and continues down
as frequency increases

Actual Function = -3dB down @ fP
+45
 (degrees)
VOUT
X100,000
0.707G = -3dB
Actual
Function
A (dB)
A = VOUT/VIN
0o
Frequency
(Hz)
0
10
+-45
100
1k
10k
100k
1M
-45o/Decade
-45o @ fP
-90
10M
 Phase = -45°/Decade Slope through fP

Decade Above fP Phase = -90° (-84.3°)

Decade Below fP Phase = 0° (-5.7°)
-90o
12
Zeros and Bode Plots
A = VOUT/VIN
L
159H
fp
100
VIN
80
Rs
100k
A (dB)
1Vp
x
+20dB/Decade
+6dB/Octave
60
20
Single Zero Circuit Equivalent
Straight-Line Approximation
1.414G = +3dB
(1/0.707)G = +3dB
Actual
Function
1
10
100
fZ
1k
10k
100k
1M o
+90
2 *
L
R
 Zero Location = fZ
10M
Frequency (Hz)
 Magnitude = +20dB/Decade Slope
+90
+45o/Decade

Slope begins at fZ and continues up as
frequency increases

Actual Function = +3dB up @ fZ
+45
 (degrees)
1
G
0
+45o @ fZ
0o
Frequency
(Hz)
0
10
-90
R
100k
fz 
40
+-45
VOUT
100
1k
10k
100k
1M
10M
 Phase = +45°/Decade Slope through fZ

Decade Above fZ Phase = +90° (+84.3°)

Decade Below fZ Phase = 0° (5.7°)
13
Capacitor - Intuitive Model
DC XC
DC < XC < Hi-f
OPEN
Hi-f XC
SHORT
frequency
controlled
resistor
XC = 1/(2fC)
14
Inductor - Intuitive Model
DC XL
DC < XL < Hi-f
SHORT
Hi-f XL
OPEN
frequency
controlled
resistor
XL = 2fL
15
Capacitor and Inductor - Impedance vs Frequency
10M
Low frequency=
High Impedance
1M
Capacitor and Inductor
Impedance vs Frequency
High frequency=
High Impedance
Impedance (ohms)
100k
10k
Capacitor Impedance
C = 159nF
Inductor Impedance
L = 159mH
1k
100
10
1
Low frequency=
Low Impedance
High frequency=
Low Impedance
100m
100m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
16
Op Amp - Intuitive Model
Vo
IN+
Ro
x1
Rin
K(f)
+
Vout
Vdiff
IN-
-
17
Op-Amp Loop Gain Model
bnetwork
RF
bnetwork
RI
b=VFB/VOUT
VOUT
VFB
VOUT
Aol
RF
+
+
VFB
VIN
RI
-
b
VOUT/VIN = Acl = Aol/(1+Aolβ)
If Aol >> 1 then Acl ≈ 1/β
Aol: Open Loop Gain
VIN
+

Aol
VOUT
β: Feedback Factor
Acl: Closed Loop Gain
18
b and 1/b
bnetwork
RF
bnetwork
RI
b=VFB/VOUT
VOUT
VFB
VOUT
RF
+
+
VIN
-
VFB
RI
 β is easy to calculate as feedback network around the Op Amp
 1/β is reciprocal of β
 Easy Rules-Of-Thumb and Tricks to Plot 1/β on Op Amp Aol Curve
 Plotting Aol Curve and 1/β Curve shows Loop Gain
19
Amplifier Stability Criteria
VOUT/VIN = Aol / (1+ Aolβ)
If: Aolβ = -1
Then: VOUT/VIN = Aol / 0  ∞
If VOUT/VIN = ∞  Unbounded Gain
Any small changes in VIN will result in large changes in VOUT which will feed
back to VIN and result in even larger changes in VOUT  OSCILLATIONS 
INSTABILITY !!
Aolβ: Loop Gain
Aolβ = -1  Phase shift of +180°, Magnitude of 1 (0dB)
fcl: frequency where Aolβ = 1 (0dB)
Stability Criteria:
At fcl, where Aolβ = 1 (0dB), Phase Shift < +180°
Desired Phase Margin (distance from +180° Phase Shift) > 45°
20
Traditional Loop Gain Test
b
Op Amp Loop Gain Model
Op Amp is “Closed Loop”
-

+
VIN
Aol
VOUT
Loop Gain Test:
b
(An Open Loop Test)
+
VTest
VIN
+

Break the Closed Loop at b
Ground VIN
Aol
VOUT
Inject AC Source, VTest, into b
Aolβ = VOUT
21
Traditional Loop Gain Test
RI
RF
bnetwork
RF
bnetwork
Short for AC
Open for DC
VFB
RI
1TF
VFB
+
1TH
-
Aol
VOUT
+
+
VIN
-
-
+
+
VIN
VOUT
Aol
VTest
-
Open for AC
Short for DC
Op Amp Loop Gain Model
SPICE Loop Gain Test:
Op Amp is “Closed Loop”
Op Amp Loop Gain Test is an “Open Loop” Test
VOUT/VIN = Aol / (1+Aolb)
SPICE finds a DC Operating Point before it does an AC
Analysis so loop must be closed for DC and open
for AC.
Break the Closed Loop at VOUT
Ground VIN  source impedance low for AC analysis
Inject: AC Source, VTest, into RF
(Inject: AC Source into High Impedance Node)
Read: Aolβ = Loop Gain = VOUT
(Read: Loop Gain from Low Impedance Node)
22
SPICE Loop Gain TestVF1
DC Analysis
VFB -25.38uV
RF 10kOhm
-279.24uV
DC Analysis
+
CT 100nF
V2 2.5V
RI 1kOhm
4
3
2
+
+
VG1
LT 1TH
VOUT -279.24uV
DC Analysis
1
5
V1 2.5V
Loop Gain (Aol ) = VOUT
= VFB
1/ = 1 / VFB
Aol = VOUT / VFB
U1 OPA2376
RF 10kOhm
CT Open
RF 10kOhm
VFB
CT Short
V2 2.5V
+
+
VFB
VG1
V2 2.5V
LT Short
RI 1kOhm
4
3
RI 1kOhm
2
+
+
VOUT
4
3
1
5
2
+
+
VOUT
1
5
V1 2.5V
U1 OPA2376
VG1
LT Open
V1 2.5V
DC Equivalent Circuit
U1 OPA2376
AC Equivalent Circuit
23
Loop Gain (Aolb) from Aol and 1/b
Open Loop Response
Aol
Plot (dB) 1/β on Op Amp Aol (dB)
100
Aolβ = Aol(dB) – 1/β(dB)
Aolβ = Aol / (1/β) = Aolβ
80
Note how Aolβ changes with frequency
Aol b
(Loop Gain)
Aol (dB)
60
40
fcl
Closed Loop Response
b
Acl

20
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
24
“Rate-of-Closure” Stability Criteria using 1/β & Aol
Aol
At fcl: Loop Gain (Aolb) = 1 (0dB)
100
Rate-of-Closure @ fcl =
(Aol slope – 1/β slope)
*20dB/decade Rate-of-Closure @ fcl =
STABLE
fcl1
80
**
b
fcl2
Aol (dB)
60
**40dB/decade Rate-of-Closure @ fcl =
UNSTABLE
*
b
40
b
*
fcl3
20
fcl4
**
b
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
25
Loop Gain (Aolb) Example
Aol
pole
pole
-----
fp1
fp2
fz1
0.15 F
fp1
100
1/b
--------zero
Loop Gain
pole
pole
pole
10k
Aol
RF
Cin
1k
-
A (dB)
80
RI
b
Aol b
60
fcl
40
STABLE
VOUT
+
+
VIN
-
Rate-of-Closure @ fcl = 40dB/decade
 UNSTABLE!
20
fz1
fp2
0
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Example 1: Note locations of poles and zeros in Aol & 1/b
26
Loop Gain (Aolβ) Plot from Aol & 1/β Plot
fp1
fp2
fz1
100
fp1
80
1/b
--------zero
Loop Gain (Aolb) Phase at fcl:
Loop Gain
pole
pole
pole
Phase Shift = -180
180
Phase Margin = 0
fp1
135
 (degrees)
A (dB)
Aol
pole
pole
-----
60
Frequency
(Hz)
90
fz1
10
40
45
100
1k
10k
100k
1M
10M
fz1
fcl
STABLE
20
0
fcl
0
1
10
100
1k
10k
100k
STABLE
1M
10M
fp2
-45
Frequency (Hz)
To Plot Aolβ from Aol & 1/β Plot:
Poles in Aol curve are Poles in Aolβ (Loop Gain)Plot
Zeros in Aol curve are Zeros in Aolβ (Loop Gain) Plot
fp2
Poles in 1/β curve are Zeros in Aolβ (Loop Gain) Plot
Zeros in 1/β curve are Poles in Aolβ ( Loop Gain) Plot
[Remember: β is the reciprocal of 1/β]
27
Example 1: Note locations of poles and zeros in Loop Gain
1/β Always = Closed Loop Response
Aol
100
VOUT/VIN = Aol/(1+Aolβ)
At fcl: Aolβ = 1  VOUT/VIN = Aol/(1+1) ~ Aol
No Loop Gain left to correct for errors
VOUT/VIN follows the Aol curve at f > fcl
RF
100k
RI
10k
80
VOUT
+
VIN
A (dB)
fcl
60
-
b
Rn
1k
Cn
16nF
+
VNOISE
40
Note:
VOUT/VIN
1/β is the AC, Small Signal,
Closed Loop, ”Noise Gain”
for the Op Amp.
20
SSBW
(Small Signal BandWidth)
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VOUT/VIN is often NOT the
same as 1/β.
28
How to Modify 1/β for Stable Circuits
ZI
INPUT Network
Rn
ZF
FEEDBACK Network
Cn
Cp
RI
Rp
RF
VOUT
+
+
VIN
-
29
1/β “First Order Analysis” for ZF
Cp
Rp
1.59nF
10k
RI
RF
1k
100k
VOUT
+
+
 1/β Low Frequency = RF/RI = 100  40dB
VIN
-
Cp = Open at Low Frequency
 1/β High Frequency = (Rp//RF)/RI ≈ Rp/RI = 10  20dB
Cp = Short at High Frequency
 Pole in 1/β when Magnitude of XCp = RF
Magnitude XCp = 1/(2∙п∙f∙Cp)
fp = 1/(2∙п∙RF∙Cp) = 1kHz
 Zero in 1/β when Magnitude of XCp = Rp
fz = 1/(2∙п∙Rp∙Cp) = 10kHz
ZF Exact equations :
1
2  Cp  (RF  Rp )
1
fz 
2  Cp  [Rp  (RI // RF)]
fp 
30
Cp
TINA SPICE: 1/β for ZF
Rp
10k
1.59nF
RI
RF
1k
100k
140
Aol
120
VOUT
+
100
+
VIN
-
Gain (dB)
80
60
1/
40
fp
fz
Lo f
Hi f
20
Lo f
Hi f
0
-20
1st Order
40dB
20dB
Actual
40.086dB
20.079dB
fp
fz
1st Order
1kHz
10kHz
Actual
917.020Hz
9.038kHz
ZF Network (fp and fz)
Aol and 1/
-40
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
31
1/β “First Order Analysis” forCn ZI
Rn
1k
15.9nF
RI
RF
10k
100k
VOUT
+
 1/β Low Frequency = RF/RI = 10  20dB
Cn = Open at Low Frequency
+
VIN
-
 1/β High Frequency = RF/(RI//Rn) ≈ RF/Rn =100  40dB
Cn = Short at High Frequency
 Zero in 1/β when Magnitude of XCn = RI
Magnitude XCn = 1/(2∙п∙f∙Cn)
fz = 1/(2∙п∙RI∙Cn) = 1kHz
 Pole in 1/β when Magnitude of XCn = Rn
fp = 1/(2∙п∙Rn∙Cn) = 10kHz
ZI Exact equations :
fp 
1
2RnCn
fz 
1
2Cn  [Rn  (RI // RF )]
32
Rn
TINA SPICE: 1/β for ZI
1k
Cn
15.9nF
RI
140
RF
10k
100k
Aol
-
120
VOUT
+
+
100
VIN
-
Gain (dB)
80
60
fp
40
1/
Hi f
Lo f
20
Lo f
Hi f
0
-20
fz
1st Order Actual
20dB
20.828dB
40dB
40.906dB
fz
fp
1st Order Actual
1kHz
999.496Hz
10kHz
9.935kHz
ZI Network (fp and fz)
Aol and 1/
-40
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
33
Stability Analysis - Method 1
(Loaded Aol & 1/b Technique)
(Riso Compensation)
Capacitive Loading on Op Amp Outputs
Unity Gain Buffer Circuits
Circuits with Gain
R3 4.99k
V-
Vin
+
V-
Will this circuit behavior
get you a raise in pay?
-
Vo
+
U1 OPA627E
+
+
Vo
R2 100k
CLoad 1uF
Vin
V+
+
+
U1 OPA627E
CLoad 1u
V+
40.00m
40m
80m
80.00m
50.00m
Vo (V)V1 20.00m
20m
Vo (V)
VF1 20.00m
20m
-10.00m
0
0.00
1.00m
-40m
-40.00m
20.00m
20m
1m
VG1
Vin (V)
10m
VG1
Vin (V)
0.00
0
0.00
0
00.00
150.00u
150u
Time (s)
Time (seconds)
300.00u
300u
0.00
0
150.00u
150u
Time (s)
Time (seconds)
35
300.00u
300u
VFB 353.900776nV
Loaded Aol
CT 1TF
LT 1TH
+
V+
140
Vtest
V+ 15V
-
-20dB/decade
120
VOUT 353.900776nV
Loaded Aol = VOUT / VFB
For AC Test VFB = Vtest
Loaded Aol = VOUT
V- 15V
fp1
Aol Pole
Low Frequency
100
80
fp2
Loaded Aol
Additional Pole
40
1/
20
+
+
U1 OPA627E
CLoad 1uF
V+
V-
60
Gain (dB)
V-
Loaded Aol due to CLoad
-40dB/decade
Rate-of-Closure
40dB/decade
0
-20
STABLE
fcl
-40
-60
-80
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
36
Loaded Aol Model
CT 1T
V+
LT 1T
Vtest
V+ 15
VFB
+
+
Ro 54
V-
Loaded Aol
Aol
-
VOUT
+
V- 15
+
U1 OPA627E
CLoad 1u
CLoad 1u
V+
VLoaded Aol = VOUT / VFB
For AC Test VFB = Vtest
Loaded Aol = VOUT
LT Open
-
-
+
+
+
CT Short
Vtest
Ro 54
Loaded Aol
Aol 1M
CLoad 1u
37
Loaded Aol Model
fp2
0
0.00
Ro 54
Aol
Loaded Aol
GainGain(dB)
(dB)
+
-20
-20.00
-40
-40.00
CLoad 1u
Loaded AOL
Pole
-60
-60.00
-80
-80.00
0
0.00
fp2 
1
2    Ro  CLoad
Phase
(degrees)
Phase [deg]
Loaded Aol Pole Equation
-45.00
-45
-90.00
-90
1.00
1
10.00
10
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency (Hz)
Frequency (Hz)
1.00M
1M
10.00M
10M
100.00M
100M
38
Loaded Aol Model
fp2
120
120.00
100
100.00
Aol
20
0
0.00
-20
-20.00
-40
-40.00
20.00
-60
-60.00
+
135.00
135
-80
-80.00
0
0.00
-45.00
-45
90
90.00
45
45.00
0 1.00
1
Aol Load
-40
-40.00
180.00
180
Phase
(degrees)
Phase [deg]
-20
-20.00
GainGain(dB)
(dB)
GainGain(dB)
(dB)
fp1
60.00
PhasePhase(degrees)
[deg]
80
60
40
40.00
80.00
0
0.00
0.00
10.00
10
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency (Hz)
GainVoltage
(dB)
(V)
120
120
100
100
10.00M
10M
100.00M
100M
-90.00
-90
1.00
1
fp1
80
80
60
60
40
40
10.00
10
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency (Hz)
Frequency (Hz)
1.00M
1M
10.00M
10M
Loaded Aol
fp2
20
20
00
-20
-20
-40
-40
180.00
180
PhaseVoltage
(degrees)
(V)
=
1.00M
1M
Frequency (Hz)
135.00
135
90
90.00
45
45.00
0
0.00
1.00
1
10.00
10
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency (Hz)
Frequency (Hz)
Note: Addition on Bode Plots = Linear Multiplication
1.00M
1M
10.00M
10M
100.00M
100M
39
100.00M
100M
VFB
LT 1TH
+
Loaded Aol –
Loop Gain & Phase
CT 1TF
V+
Vtest
V+ 15V
V-
VOUT
Loop Gain (Aol ) = VOUT
V- 15V
+
+
U1 OPA627E
CLoad 1uF
V+
V-
STABLE
Phase Margin at fcl
40
Riso Compensation
Riso will add a zero in the Loaded Aol Curve
V+
VV+ 15V
Riso 6Ohm
-
+
U1 OPA627E
VIN
V- 15V
VOUT
+
+
CLoad 1uF
V+
VOA
V-
41
Riso Compensation
Results
CT 1TF
+
V-
Vtest
V+ 15V
Riso 6Ohm
-
140
U1 OPA627E
Loaded Aol with Riso Compensation
Loaded Aol = VOA
fp1
Aol Pole
Low Frequency
80
V+
VOA
V-
-40dB/decade
60
fp2
Loaded Aol
Additional Pole
40
1/
20
+
CLoad 1uF
V- 15V
100
VOUT
+
-20dB/decade
120
Gain (dB)
LT 1TH
V+
fz1
Loaded Aol
Riso Compensation
Additional Zero
-20dB/decade
Rate-of-Closure
20dB/decade
0
-20
fcl
STABLE
-40
-60
-80
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
42
Riso Compensation Theory
V+
VOA
V-
V+ 15
LT 1T
-
Riso 6
VOUT
+
V- 15
+
U1 OPA627E
CLoad 1u
V+
Vtest
V-
Ro 54
+
+
CT 1T
Loaded Aol
Aol
Riso 6
CLoad 1u
LT Open
Loaded Aol
-
-
+
+
+
CT Short
Vtest
Ro 54
Riso 6
VOUT
Aol 1M
CLoad 1u
43
Riso Compensation Theory
0
0.00
fp2
Loaded Aol
Aol
Riso 6
fz1
GainGain(dB)
(dB)
+
Ro 54
-20.00
-20
-40
-40.00
CLoad 1u
Loaded Aol (s) 
1  CLoad  Riso  s
1  (Ro  Riso)  CLoad  s
-45.00
-45
-90.00
-90
1.00
1
Pole :
fp2 
Phase
(degrees)
Phase [deg]
Transfer Function
0
0.00
1
2(Ro  Riso)  CLoad
10.00
10
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency (Hz)
Frequency (Hz)
1.00M
1M
10.00M
10M
100.00M
100M
Zero :
fz1 
1
2  Riso  CLoad
44
Riso Compensation Theory
GainGain(dB)
(dB)
fp1
Aol
Aol Load
-40
-40.00
180.00
180
Phase
(degrees)
Phase [deg]
fz1
-20.00
-20
20
0
0.00
-20
-20.00
-40
-40.00
20.00
+
135.00
135
90
90.00
45
45.00
0 1.00
1
fp2
GainGain(dB)
(dB)
80
60
60.00
40
40.00
80.00
0
0.00
0
0.00
Phase
(degrees)
Phase [deg]
120
120.00
100
100.00
-90.00
-90
1.00
1
0.00
10.00
10
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency (Hz)
Frequency (Hz)
120.00
120
100.00
100
1.00M
1M
10.00M
10M
-45.00
-45
100.00M
100M
fp1
80
60.00
60
40.00
40
GainGain(dB)
(dB)
100.00
100
1.00k
1k
10.00k
100.00k
10k
100k
Frequency
(Hz)
Frequency (Hz)
1.00M
1M
10.00M
10M
Loaded Aol
80.00
fz1
fp2
20
0.00
0
-20.00
-20
-40.00
-40
20.00
180.00
180
PhasePhase(degrees)
[deg]
=
10.00
10
135.00
135
90.00
90
45.00
45
0.00
0
1.00
1
10.00
10
100.00
100
1.00k
1k
10.00k
10k
Frequency (Hz)
100.00k
100k
Frequency (Hz)
Note: Addition on Bode Plots = Linear Multiplication
1.00M
1M
10.00M
10M
100.00M
100M
45
100.00M
100M
Riso Compensation Design Steps
1) Determine fp2 in Loaded Aol due to CLoad
A) Measure in SPICE with CLoad on Op Amp Output
2) Plot fp2 on original Aol to create new Loaded Aol
3) Add Desired fz2 on to Loaded Aol Plot for Riso Compensation
A) Keep fz1 < 10*fp2 (Case A)
B) Or keep the Loaded Aol Magnitude at fz1 > 0dB (Case B)
(fz1>10dB will allow for Aol variation of ½ Decade in Unity Gain Bandwidth)
4) Compute value for Riso based on plotted fz1
5) SPICE simulation with Riso for Loop Gain (Aolb) Magnitude and Phase
6) Adjust Riso Compensation if greater Loop Gain (Aolb) phase margin desired
7)
Check closed loop AC response for VOUT/VIN
A) Look for peaking which indicates marginal stability
B) Check if closed AC response is acceptable for end application
8)
Check Transient response for VOUT/VIN
A) Overshoot and ringing in the time domain indicates marginal stability
B) Determine if settling time is acceptable for end application
46
CT 1TF
1),2) Loaded Aol and fp2
LT 1TH
+
V+
V-
Vtest
V+ 15V
Riso 0Ohm
-
U1 OPA627E
VOUT
+
+
CLoad 2.9nF
V- 15V
Loaded Aol = VOA
V+
VOA
V-
47
Case A, CLoad=1uF, fp2=2.98kHz
Case B, CLoad=2.9nF, fp2=983.37kHz
3) Add fz1 on Loaded Aol
140
120
100
Loaded Aol
Add Riso Compensation
2.98kHz
80
Voltage (V)
60
fp2
Case B
983.37kHz
CLoad=2.9nF
fp2
Case A
CLoad=1uF
40
20
fz1
29.8kHz
Case A
CLoad=1uF
0
4.07MHz
fz1
Case B
CLoad=2.9nF
-20
-40
-60
-80
1
10
100
Case A, CLoad=1uF, fz1=29.8kHz
Case B, CLoad=2.9nF, fz1=4.07MHz
1k
10k
Frequency (Hz)
100k
1M
10M
48
4) Compute Value for Riso
Case A, CLoad=1uF, fz1=29.8kHz
Case B, CLoad=2.9nF, fz1=4.07MHz
Zero :
Zero, Case A, CLoad  1F, fz1  29.8kHz :
1
2  Riso  CLoad
1
Riso 
2  fz1 CLoad
1
2  Riso  CLoad
1
Riso 
 5.34  use 5.36Ω
2  29.8kHz  1F
fz1 
fz1 
Zero, Case B, CLoad  2.9nF, fz1  4.07MHz :
1
2  Riso  CLoad
1
Riso 
 13.48  use 13.7Ω
2  4.07MHz  2.9nF
fz1 
49
CT 1TF
5),6) Loop Gain, Case A
LT 1TH
+
V+
V-
Vtest
V+ 15V
Riso 5.36Ohm
-
U1 OPA627E
VOUT
+
+
CLoad 1uF
V- 15V
V+
VOA
Loop Gain (Aol ) = VOA
V-
Phase Margin at fcl = 87.5 degrees
50
CT 1TF
5),6) Loop Gain, Case B
LT 1TH
+
V+
V-
Vtest
V+ 15V
Riso 13.7Ohm
-
U1 OPA627E
VOUT
+
+
CLoad 2.9nF
V- 15V
V+
VOA
Loop Gain (Aol ) = VOA
V-
Phase Margin at fcl = 54 degrees
51
V+
7) AC VOUT/VIN, Case A
VV+ 15V
Riso 5.36Ohm
-
U1 OPA627E
VOUT
+
+
+
CLoad 1uF
V- 15V
VIN
V+
VOA
V20
VOA
-3dB=1.58MHz
Gain (dB)
0
VOUT/VIN
Riso Compensation
Case A, CLoad=1uF
-20
VOUT
-3dB=30.44kHz
-40
-60
-80
0
Phase [deg]
-45
-90
-135
-180
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
52
V+
8) Transient Analysis, Case A
VV+ 15V
Riso 5.36Ohm
-
U1 OPA627E
VOUT
+
+
10.00m
+
VIN
CLoad 1uF
V- 15V
VOUT / VIN
Transient Analysis
Case A, CLoad=1uF
VIN
V+
VOA
V-
-10.00m
10.27m
VOA
-10.27m
10.01m
VOUT
-10.01m
0
500u
1m
Time (s)
2m
2m
53
Riso Compensation: Key Design Consideration
Accuracy of VOUT depends on Load Current
Light Load Current
V+
VOA 5V
V-
ILoad 4.970179mA
V+ 15V
-
+
Riso 6Ohm
+
U1 OPA627E
VIN 5V
+
A
CLoad 1uF
V+
V2 15V
VOUT 4.970179V
RLoad 1kOhm
V-
V+
Heavy Load Current
VOA 5V
V-
ILoad 24.271845mA
-
V+ 15V
+
VIN 5V
Riso 6Ohm
+
U1 OPA627E
V+
+
A
CLoad 1uF
VOUT 4.854369V
RLoad 200Ohm
V2 15V
V54
Stability Analysis - Method 2
(Aol and1/bTechnique)
(CF Compensation)
RI 180kOhm
RF 180kOhm
+
Large Input Resistance &
Input Capacitance
VIN
V2 18V
10.00m
+
VOUT
+
U1 OPA140
V1 18V
VIN
-10.00m
27.04m
Do you want this hidden in
your product - in production?
VOUT
-26.95m
990.00u
1.01m
1.03m
Time (s)
1.05m
56
VFB
RI 180kOhm
CT 1TF
RF 180kOhm
+
Aol and 1/b
LT 1TH
140
Aol = Vout/VFB
1/ = 1/VFB
Loop Gain (Aol ) = Vout
Aol and 1/
Aol
VG1
V2 18V
120
+
100
Vout
+
U1 OPA140
V1 18V
Voltage (V)
80
60
40
20
Rate-of-Closure
40dB/decade
1/
fcl
0
fz1
104kHz
-20
STABLE
-40
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
57
Op Amp Input Capacitance
VEE 18V
INCcm- 7pF
Cdiff 10pF
IN+
+
U1 OPA140
VOUT
+
Ccm+ 7pF
OPA140 - Input Capacitance
VCC 18V
58
Equivalent Input Capacitance and b
RF 180kOhm
VFB
VOUT
1 VOUT

b
VFB
+
RI 180kOhm
b
VIN
V1 18V
Ccm- 7pF
Cdiff 10pF
+
VOUT
+
U2 OPA140
VOUT
RF 180kOhm
VFB
V2 18V
Ccm+ 7pF
Cin_eq 17pF
RI 180kOhm
VFB
RI 180kOhm
RF 180kOhm
Cin_eq 17pF
V3 18V
+
VOUT
+
U3 OPA140
V4 18V
59
Equivalent Input Capacitance and b
VOUT
(Set to 1V)
RF 180kOhm
b
1/β Computation :
1 RF (RI // X

β
RI // X
Cin_eq
VFB
)
Cin_eq 17pF
RI 180kOhm
Cin_eq




1
s 
  Cin _ eq  RF  RI
 RF  RI  

Cin _ eq  


1
RF  RI  



 (after simplification)
β
RI
1
RF  RI
RF
180k
DC 
 1
 1
 2  6dB
β
RI
RI
180k
1
1
1
zero: fz1 

 104kHz
β
2π  Cin_eq  (RF // RI) 2π  17pF  (180k // 180k)
60
CF Compensation Design Steps
1) Determine fz1 in 1/b due to Cin_eq
A) Measure in SPICE
OR
B) Compute by Datasheet CDIFFand CCM and Circuit RF and RI
2) Plot 1/b with fz1 on original Aol
3) Add Desired fp1 on 1/b for CF Compensation
A) Keep fp1 < 10*fz1
B) Keep fp1 < 1/10 * fcl
4) Compute value for CF based on plotted fp1
5) SPICE simulation with CF for Loop Gain (Aolb) Magnitude and Phase
6) Adjust CF Compensation if greater Loop Gain (Aolb) phase margin desired
7) Check closed loop AC response for VOUT/VIN
A) Look for peaking which indicates marginal stability
B) Check if closed AC response is acceptable for end application
8) Check Transient response for VOUT/VIN
A) Overshoot and ringing in the time domain indicates marginal stability
61
1),2),3) Plot Aol, 1/b,
Add fp1 in 1/b for Stability
For fp1:
fp1 < 10 * fz1
fp1 < 1/10 * fcl
140
Aol and 1/
Input Capacitance Compensation
Aol
120
100
Gain (dB)
80
60
40
Add fp1
316kHz
1/
20
Hi-f = 15dB
Lo-f = 6dB
0
New fcl
fz1
104kHz
-20
-40
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
62
CF 2.7pF
4) Compute value of CF
RI 180kOhm
RF 180kOhm
+
VOUT
CF 2.7pF
VIN
RF 180kOhm
-
1/β Computation :
1 (RF// X )  (RI // X

RI // X
β
CF
V3 18V
Cin_eq 17pF
VFB
Cin_eq
)
Cin_eq 17pF
RI 180kOhm
Cin_eq
+
VOUT
+
U3 OPA140
V4 18V




1
Cin_eq  CF  s 

RI

RF



Cin_eq  CF 



1
 RF  RI 
 (after simplification)

1 
β

CF  s 
 RF  CF 
180k
RF
RF  RI
1
 2  6dB
 1
 1
DC 
180k
RI
RI
β
1
1
1
 89.77kHz

zero : fz1 
2  (RF // RI)  Cin_eq // CF  2  (180k // 180k )  17pF // 2.7pF
β
1
1
1
 327.48kHz

pole : fp1 
2π  CF  RF 2π  2.7pF  180k
β
63
CF 2.7pF
VFB
CT 1TF
RF 180kOhm
Aol = Vout/VFB
1/ = 1/VFB
Loop Gain (Aol ) = Vout
+
RI 180kOhm
LT 1TH
5), 6) Loop Gain Check
Vtest
V2 18V
+
Vout
+
U1 OPA140
V1 18V
Phase Margin at fcl = 68 degrees
64
CF 2.7pF
7) VOUT/VIN AC Response
RF 180kOhm
+
RI 180kOhm
VIN
V2 18V
+
VOUT
+
U1 OPA140
V1 18V
0
VOUT/VIN
CF Compensation
VOUT
-3dB=394.5kHz
Gain (dB)
-20
-40
-60
180
Phase [deg]
135
90
45
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
65
CF 2.7pF
8) Transient Analysis
RF 180kOhm
+
RI 180kOhm
VIN
V2 18V
+
VOUT
+
10.00m
U1 OPA140
V1 18V
VOUT / VIN
Transient Analysis
VIN
-10.00m
10.11m
VOUT
-9.98m
0
500u
1m
Time (s)
2m
2m
66