Transcript EE 5340 Semiconductor Device Theory Lecture 25 – Spring 2011 Professor Ronald L.

EE 5340
Semiconductor Device Theory
Lecture 25 – Spring 2011
Professor Ronald L. Carter
[email protected]
http://www.uta.edu/ronc
Ideal 2-terminal
MOS capacitor/diode
conducting
gate,
area = LW
Vgate
-xox
SiO2
0
L
silicon substrate
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Vsub
y
0
tsub
x 2
MOS surface states**
p- substr = n-channel
VGS
s
VGS < VFB < 0
s < 0
Accum.
ps > N a
VGS = VFB < 0
s = 
Neutral
ps = N a
VFB < VGS
s > 0
Depletion
ps < N a
VFB < VGS < VTh
s = |p|
Intrinsic ns = ps = ni
VGS < VTh
s > |p|
Weak inv ni< ns < Na
VGS = VTh
s = 2|p|
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Surf chg Carr Den
O.S.I.
ns = Na
3
MOS Bands at OSI
p-substr = n-channel
Fig 10.9*
qp
2q|p|
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xd,max
4
Equivalent circuit
for accumulation
• Accum depth analogous to the accum
Debye length = LD,acc = [eVt/(qps)]1/2
• Accum cap, C’acc = eSi/LD,acc
• Oxide cap, C’Ox = eOx/xOx
C’Ox
• Net C is the series comb
1
1
1


C'tot C'acc C'Ox
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C’acc
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Equivalent circuit
for Flat-Band
• Surface effect analogous to the extr
Debye length = LD,extr = [eVt/(qNa)]1/2
• Debye cap, C’D,extr = eSi/LD,extr
• Oxide cap, C’Ox = eOx/xOx
C’Ox
• Net C is the series comb
1
1
1


C'tot C'D,extr C'Ox
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C’D,extr
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Equivalent circuit
for depletion
• Depl depth given by the usual formula
= xdepl = [2eSi(Vbb)/(qNa)]1/2
• Depl cap, C’depl = eSi/xdepl
• Oxide cap, C’Ox = eOx/xOx
• Net C is the series comb
1
1
1


C'tot C'depl C'Ox
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C’Ox
C’depl
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Equivalent circuit
above OSI
• Depl depth given by the maximum
depl = xd,max = [2eSi|2p|/(qNa)]1/2
• Depl cap, C’d,min = eSi/xd,max
• Oxide cap, C’Ox = eOx/xOx
C’Ox
• Net C is the series comb
1
1
1


C'tot C'd,min C'Ox
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C’d,min
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Differential charges
for low and high freq
high freq.
From Fig 10.27*
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Ideal low-freq
C-V relationship
Fig 10.25*
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Comparison of low
and high freq C-V
Fig 10.28*
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Effect of Q’ss on
the C-V relationship
Fig 10.29*
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Flat band condition
(approx. scale)
If
Ec  Efp  0.85eV
Then
Efm  Efp  0.8eV
 VFB   fm   fp
Al
q(m-cox)=
3.15 eV
EFm
 0.8V  Vg  Vs
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Ev
p-Si
q(cox-cSi)=3.1eV
Ec,Ox
Eg,ox
~8eV
 MS
for flat - band cond
SiO2
qfp=
3.95eV
Ec
EFi
Ev EFp
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Flat-band parameters
for n-channel (p-subst)
p  substrate : VFB  ms
Q'ss

C'Ox
e Ox
C'Ox 
, Q'ss is the Ox/Si chg den
xOx
For a n  poly - Si gate,  s  m  c s
ms
 NcNa 
 Eg
 Na  
 Vt ln 2     Vt ln    0
 ni  
 2q
 ni 
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Flat-band parameters
for p-channel (n-subst)
n  substrate : VFB  ms
Q'ss

(no change)
C'Ox
eOx
C'Ox 
, Q'ss is the Ox/Si chg den
xOx
For a p  poly - Si gate,  s  m  c s 
 NvNd   Eg
 Nd  
ms  Vt ln 2     Vt ln    0
ni   2q
 ni  
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Eg
q
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Typical ms values
ms
(V)
Fig 10.15*
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NB (cm-3)
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Flat band with oxide
charge (approx. scale)
Al
If a charge Q'ss is
at the Ox/Si bound,
then at FB cond a
q(Vox)
+<--Vox-->-
charge Q'm  Q'ss is q(m-cox)
on the gate surface
E
'
Qss
1 dEc VOx


Ex 
e Ox q dx xOx
VFB   ms  VOx   ms
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'
Qss
 '
COx
SiO2
Fm
q(VFB)
p-Si
Ec,Ox q( -c )
fp ox
Ex
Eg,ox
Ec
~8eV
EFi
EFp
Ev
VFB= VG-VB, when
Si bands are flat
Ev
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Inversion for p-Si
Vgate>VTh>VFB
EOx,x
Vgate> VFB
VOx

0
xOx
 Induced ESi
 0 depletes
 Induced ESi
above threshold
for inversion
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EOx,x> 0
e- e- e- e- eDepl Reg
Acceptors
Vsub = 0
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Approximation concept
“Onset of Strong Inv”
• OSI = Onset of Strong Inversion
occurs when ns = Na = ppo and VG = VTh
• Assume ns = 0 for VG < VTh
• Assume xdepl = xd,max for VG = VTh and
it doesn’t increase for VG > VTh
• Cd,min = eSi/xd,max for VG > VTh
• Assume ns > 0 for VG > VTh
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MOS Bands at OSI
p-substr = n-channel
Fig 10.9*
qp
2q|p|
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xd,max
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Computing the D.R.
W and Q at O.S.I.
Ex
Emax

2eSi 2  p
xd ,max 
q
dEx

Na
dx
eSi

qNa
area  2  p
x
Q'd,max  qNa xd,max
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Calculation of the
threshold cond, VT
The threshold condition is reached
when the surface is inverted. The
depletion region has reached the
value of xd,max and the extra charge
is Q'd,max  qNBxd,max (n - sub, p - sub)
VT  VFB  V, where V is the voltage
added to induce  Q'd,max across the Ox
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Equations for
VT calculation
p, n  substr : VT  VFB  2p,n 
'
Qd,max
C'Ox
 Nd 
 ni 
p  Vt ln    0, n  Vt ln    0,
 Na 
 ni 
Q'd,max   qNa,d xd,max , xd,max 
2e 2p,n
qNa,d
V  0 for p - substr,  0 for n - substr
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Fully biased n-MOS
capacitor
VG
Channel if
VG > VT
VS
EOx,x> 0
n+ e- e- e- e- e- e-
n+
VD
p-substrate
Vsub=VB
Depl Reg
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0
Acceptors
L
y
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MOS energy bands at
Si surface for n-channel
Fig 8.10**
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Computing the D.R.
W and Q at O.S.I.
Ex
Emax
xd ,max 

2eSi 2  p  (VB VS )

qNa
q
dEx

Na
dx
eSi
area  2  p  (VB VS )
x
Qd,max  qNa xd,max
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Q’d,max and xd,max for
biased MOS capacitor
Fig 8.11**
xd,max
(mm)
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Q'd,max
q
-2
(cm )
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Fully biased nchannel VT calc
p  substrate : VG, at threshold  VT
VT  VC  VFB  2p 
Q'd,max
 VFB  V
C'Ox
 ni 
p  Vt ln   0, Q'd,max  qNa xd,max ,
 Na 
xd,max 
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

2e 2 p  VB  VC 
qNa
, V  0
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n-channel VT for
VC = V B = 0
Fig 10.20*
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Fully biased pchannel VT calc
n  substrate : VG, at threshold  VT
VT  VC  VFB  2n 
Q'd,max
C'Ox
 VFB  V
 Nd 
n  Vt ln   0, Q'd,max  qNdxd,max ,
 ni 
2e2 n  VC  VB 
xd,max 
, V  0
qNd
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p-channel VT for
VC = V B = 0
Fig 10.21*
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n-channel enhancement
MOSFET in ohmic region
Channel
VS = 0
Depl Reg
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0< VT< VG
EOx,x> 0
n+ e-e- e- e- e-
p-substrate
VB < 0
0< VD< VDS,sat
n+
Acceptors
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Conductance of
inverted channel
•
•
•
•
•
Q’n = - C’Ox(VGC-VT)
n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2)
The conductivity sn = (n’s/t) q mn
G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so
I = V/R = dV/dR, dR = dL/(n’sqmnW)
L
VD
0
VS
I  dL   C'Ox VG  VC   VT  mnWdV
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Basic I-V relation
for MOS channel
WmnC'Ox
2
ID 
2VG  VT VDS  VDS
, VDS  VG  VT
2L
At VDS  VDS,sat  VG  VT , Q'n y  L   0  Sat.


so let ID be given by ID VDS,sat ,
for VDS  VDS,sat  VG  VT so
ID  ID,sat
Wmn C'Ox
2
VG  VT 

2L
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I-V relation for
n-MOS (ohmic reg)
mnC'Ox W
2


ID 
2VG  VT VDS  VDS
. Note
2
L
VDS  VG  VT  VDS,sat ,
result is non - physical.
At VDS,sat , n's, y L  0
ID
ID,sat
for
ohmic
non-physical
assume that channel curr.
is const for VDS  VDS,sat
ID,sat
mnC'Ox W
VGS  VT 2

2
L
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saturated
VDS,sat
VDS
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References
* Semiconductor Physics & Devices, by
Donald A. Neamen, Irwin, Chicago,
1997.
**Device Electronics for Integrated
Circuits, 2nd ed., by Richard S. Muller
and Theodore I. Kamins, John Wiley
and Sons, New York, 1986
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Computing the D.R.
W and Q at O.S.I.
Ex
Emax

2eSi 2  p
xd ,max 
q
dEx

Na
dx
eSi

qNa
area  2  p
x
Q'd,max  qNa xd,max
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