Transcript Udo Kebschull Kirchhoff Institute for Physics Computer Engineering

ROC Status
and
Future Plans
Udo Kebschull
Kirchhoff Institute for Physics
Computer Engineering
University Heidelberg, Germany
Phone:
+49 6221 54 9800
Fax:
+49 6221 54 9809
Email:
[email protected]
WWW:
www.ti.uni-hd.de
© U. Kebschull
Computer Engineering / TI
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Agenda
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What is SysCore?
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ROC Status
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Future Plans
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Summary
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Computer Engineering / TI
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What is SysCore?
SysCore Architecture
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Abstract definition of design
rules, enabling
– Linux
– Improved radiation tolerance
through configuration refresh
– Various FPGA
configuration possibilities
● FLASH
● Standard USB Cable
● Remote (Ethernet)
● Xilinx Cable
– Maximum I/O
flexibility
– MGT operation
Usable for many applications
such as as ROCs and others
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Computer Engineering / TI
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What is SysCore?
SyCore Board Family
SysCore V1
© U. Kebschull
SysVore V2
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SysCore V3
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What is SysCore?
SysCore V1
Test and bring-up
● N-XYTER ROC
Prototype
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SysVore V2
N-XYTER ROC
● FEET ROC
development
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SysCore V3
CBM-XYTER ROC
● FEET ROC
● DCS-Board
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SysCore Applications
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Computer Engineering / TI
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What is SysCore?
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SysCore is
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Abstract architecture
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Family of Boards
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Enabling various features
Implementing SysCore Architecture
List of Applications
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© U. Kebschull
SysCore Architecture
SysCore Board
N-XYTER ROC
FEET ROC
DCS Board
etc.
Special connectors
FPGA-Firmware
APIs and Libraries
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Current Status
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SysCore Architecture
– Based on Virtex 4 FX20 or FX60
– RS232, DDR-RAM, SD-Card, Ethernet and USB
– Automatic configuration from Flash-RAM at
start-up
– Remote Configuration
● USB, Xilinx Programmer cable and Ethernet
SysCore Board V1 and V2
– Linux on PPC, MicroBlaze, Leon3
– Configuration refresh
– Ethernet data transfer to PC
ROC
– N-XYTER read-out API
– Multiple n-XYTERs and ADCs can
be utilized
– Time synchronization of multiple ROC
ROC was used for test
beam setups
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Computer Engineering / TI
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Future Plans
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SysCore Board V2 based improvements
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Further development of the n-XYTER ROC
➔ Norbert Abel
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FEET ROC firmware and API
➔ Sebastian Manz
Development of the SysCore Board V3 based on
Virtex 5 or new Spartan 6
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Development of the CBM-XYTER ROC
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Development of the FEET ROC starter kit
➔ Dirk Gottschalk
Radiation tolerance
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Development of radiation tolerant FPGA IP cores
➔ Heiko Engel
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Investigation on eASICS
➔ Jano Gebelein
Development of a CBM-DCS Board running Epics
➔ N. N.
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Computer Engineering / TI
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© U. Kebschull
Computer Engineering / TI
2009 September Beamtime
Beamtime preparation (July + August)
Additional Functionality (June)
MGTs (May)
New Peek&Poke-Concept (April)
Debugging / Support (March & April)
March 2009
Complete Porting
Debugging / Support
Redevelopment of the
PPC-System
2008 September Beamtime
SysCore Board V2: N-XYTER ROC Improvement for 2009
ISE 8.2i & EDK 8.2i
ISE 10.1i & EDK 10.1i
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SysCore Board V3: Ideas and Improvements
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SysCore V3 is a new implementation of SysCore
Architecture
– Based on Xilinx Virtex 5 or Spartan 6 devices
We want to avoid a multitude of slightly different ROC
during R&D phase
– flexibility and fast adaptability to new ideas is
prime goal
– a single row of B2B connectors will replace the current
user port, extra connectors, and expansion connectors
Core board with a generic interface
– plug-on adapters for the different use cases
– supports efficiently all FEB and cabling solutions
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Xilinx Spartan 6
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45 nm process technology
Virtex-like 6 input LUTs
ICAP interface for dynamic partial (re)-configuration
Claimed to be low cost, low power
Integrated memory controller
– DDR, DDR2 and DDR3
Integrated PCIe Interface
DSP slices
LXT series include up to eight 3.125 GB/s Transceivers
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Computer Engineering / TI
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eASIC
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Nextreme-2T
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Mixture of FPGA and ASIC
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LUT for Logic
Fixed wires
Claims
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Density Advantage - 3X higher density than 40nm FPGAs
Performance Advantage - 700MHz logic fabric
Memory Advantage - including 600MHz block RAMs, register
files and ViaROM
High Speed I/O Advantage - Up to 56, 6.5Gbps serial
transceivers and 1.25Gbps LVDS
Power Consumption Advantage - Up to 80% lower power
consumption than FPGAs
DSP Advantage - Up to 2.4 TeraMACs/s DSP performance
without dedicated DSP multipliers
Embedded Processing Advantage - Choose from ARM,
Tensilica, OpenRISC or LEON processors
Design Flow Advantage - Approximately 4-10 weeks
from RTL to tape-out
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Computer Engineering / TI
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eASIC
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But
– Availability?
– Cost?
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Claimed to be lower than FPGA for 500+ units
Radiation Tolerance?
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© U. Kebschull
No statements yet
We think it will be better than FPGA
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SysCore based DCS Board
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SysCore architecture was designed to supports OS
Running Linux 2.4 and 2.6 kernels on PPC and a variety of
soft CPUs
– Leon3
– Microblaze
– MIPS-like Processor
EPICs is the selected experiment control system
EPICs is ported to RTEMs
RTEMS
– Open source Real Time Operating Systems
– GNU Licence
– Easy to port
© U. Kebschull
Computer Engineering / TI
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Summary
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SysCore architecture and SysCore boards
can build the base for a variety of ROC applications
SysCore can serve as a DCS board
With FPGA based radiation tolerance techniques SysCore
boards can be used for test beam set-ups and in several
CBM sub detectors
New Spartan 6 based SysCore V3 seems to be a low cost
solution for higher volumes
Further investigations required!
© U. Kebschull
Computer Engineering / TI
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ROC Status and Future Plans
Thanks for your attention!
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Questions?
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© U. Kebschull
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Computer Engineering / TI
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