Structura pipeline a unui procesor MIPS Considerații preliminare Tip instructiune Faza de fetch Citire registri Operatie ALU Acces la date Scriere registru Timp total Load word (lw) 200ps 100ps 200ps 200ps 100ps 800ps Stoare word (sw) 200ps 100ps 200ps 200ps R-format (add, sub...) 200ps 100ps 200ps Branch (beq) 200ps 100ps 200ps 700ps 100ps 600ps 500ps lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) t Considerații preliminare IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg Considerații.
Download ReportTranscript Structura pipeline a unui procesor MIPS Considerații preliminare Tip instructiune Faza de fetch Citire registri Operatie ALU Acces la date Scriere registru Timp total Load word (lw) 200ps 100ps 200ps 200ps 100ps 800ps Stoare word (sw) 200ps 100ps 200ps 200ps R-format (add, sub...) 200ps 100ps 200ps Branch (beq) 200ps 100ps 200ps 700ps 100ps 600ps 500ps lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) t Considerații preliminare IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg Considerații.
Structura pipeline a unui procesor MIPS 1 Considerații preliminare Tip instructiune Faza de fetch Citire registri Operatie ALU Acces la date Scriere registru Timp total Load word (lw) 200ps 100ps 200ps 200ps 100ps 800ps Stoare word (sw) 200ps 100ps 200ps 200ps R-format (add, sub...) 200ps 100ps 200ps Branch (beq) 200ps 100ps 200ps 200 600 0 400 800 1000 700ps 100ps 600ps 500ps 1200 1400 1600 1800 2000 2200 2400 lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) 2 t Considerații preliminare IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg 3 Considerații preliminare IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg IM Reg ALU DM Reg 4 Considerații preliminare 0 lw $1, 100($0) 200 IF lw $2, 200($0) 400 lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) 1000 1200 EX MEM WB IF ID EX MEM WB IF ID EX MEM 400 200 IF 800 ID lw $3, 300($0) 0 600 1400 1600 1800 2000 2200 2400 t WB 600 800 ID EX MEM IF ID EX IF ID 1000 t 1200 WB MEM WB EX MEM WB 5 Etapele pipeline ID: Instruction decode/ register file read IF:Instruction fetch Ex: Execute/ adress calculation MEM:Memory access WB: write back 0 1 M u x 4 S S Shift left 2 Memorie instructiuni Registri Instr[25:21] Data memory Read register 1 Read data 1 Instr[20:16] cod PC adresa Read register 2 0 Instr[15:11] M u 1x Write register Read data 2 Write data Instr[15:0] 16 Signextend A Zero L U Address 0M u 1x Read data 1 0 Write data 32 6 M u x Calea de date pentru pipeline 1 M u x IF/ID ID/EX MEM/WB EX/MEM 0 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] Instr[15:11] PC cod adresa Read register 2 Write register Read data 2 Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend 7 M u x Execuţia instrucţiunii lw – IF IF/ID ID/EX MEM/WB EX/MEM 0 M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Read register 1 Data memory Read data 1 Instr[20:16] PC Read register 2 Write register Read data 2 cod adresa Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend Instr[20:16] 8 M u x Execuţia instrucţiunii lw - ID IF/ID ID/EX MEM/WB EX/MEM 0 M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] PC Read register 2 Write register Read data 2 cod adresa Write data Instr[15:0] Instr[20:16] Signextend A Zero L U Address 0M u 1x Read data 1 0 Write data M u x Execuţia instrucţiunii lw - EX IF/ID 0 ID/EX MEM/WB EX/MEM M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] PC Read register 2 Write register Read data 2 cod adresa Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend 10 M u x Execuţia instrucţiunii lw - MEM IF/ID ID/EX MEM/WB EX/MEM 0 M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] PC Read register 2 Write register Read data 2 cod adresa Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend 11 M u x Execuţia instrucţiunii lw - WB IF/ID ID/EX MEM/WB EX/MEM 0 M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] PC Read register 2 Write register Read data 2 cod adresa Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend 12 M u x Execuţia instrucţiunii sw – MEM IF/ID ID/EX MEM/WB EX/MEM 0 M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] PC Read register 2 Write register Read data 2 cod adresa Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend 13 M u x Execuţia instrucţiunii sw – WB IF/ID ID/EX MEM/WB EX/MEM 0 M u x 1 4 S S Shift left 2 Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 Instr[20:16] Instr[15:11] PC cod adresa Read register 2 Write register Read data 2 Write data Instr[15:0] A Zero L U Address Read data 1 0M u 1x 0 Write data Signextend 14 M u x Execuția pipline a unei secvențe de instrucțiuni independente lw $10, 20($1) sub $11, $2, $3 add $12, $3, $4 lw $13, 24($1) add $14, $5, $6 IM DM Reg IM DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg Reg Reg DM Reg 15 Controlul ȋn execuția pipeline instructiune W B I F / I D M control W B E X I D / E X M W B E X / M E M M E M / W B 16 Controlul ȋn execuția pipeline - detalii ID/EX MEM/WB EX/MEM W B Instr[31:26] RegWrite M control W B ALUOp 4 E X MemWrite M W B MemRead IF/ID S S PCSrc Shift left 2 MemWrite MemtoReg 4 AluSrc RegDst RegWrite Memorie instructiuni Instr[25:21] Registri Data memory Read register 1 Read data 1 PCSrc Instr[20:16] Read register 2 AluSrc 0 M u x PC cod Read data 2 adresa Address Read data 0M u 1x Write register 1 A Zero L U 1 0 M u x Write data Write data Instr[15:0] Instr[20:16] Instr[15:11] Signextend 6 RegDst 0M ALU control MemRead ALUOp u 1x 17 Hazardul ȋn execuția pipeline Prin hazard ȋn funcționarea pipeline vom ȋnțelege acele situații când execuția unei noi instrucțiuni nu se poate realiza pe următorul ciclu. Pot fi puse ȋn evidență trei tipuri de hazard: Hazard structural (structural hazard) – atunci când hardware-ul nu suportă execuția unei anumite combinații de instrucțiuni ȋn acelaşi ciclu. În cazul procesoarelor MIPS setul de instrucțiuni a fost astfel gandit ȋncât să evite acest tip de hazard atât timp cât există o memorie de instrucțiuni şi o memorie de date. Hazard al datelor (data hazard) – atunci când execuția unei instrucțiuni este blocată deoarece instrucțiunile anterioare nu i-au furnizat ȋncă datele necesare. Hazard la citirea din memorie (load-use data hazard) – o formă specifică de hazard al datelor ȋn care data care se ȋncarcă din memorie nu este ȋncă disponibilă pentru următoarea instrucțiune. Hazard al controlului (control hazard, branch hazard) - atunci când instrucțiunea executată nu este instrucțiunea corectă (ȋn cazul instrucțiunilor de ramificare). 18 Hazardul datelor ȋn execuția pipeline Se datorează dependenței execuției unei instrucțiuni de rezultatul execuției unei instrucțiuni anterioare ȋncă nefinalizată. add $s0, $t0, $t1 sub $t2, $s0, $t3 t add $s0, $t0, $t1 IM sub $t2, $s0, $t3 DM Reg IM Reg DM Reg Reg t add $s0, $t0, $t1 sub $t2, $s0, $t3 IM DM Reg IM Reg Reg DM Reg 19 Hazardul datelor ȋn execuția pipeline t lw $s0, 20($t1) IM DM Reg Reg bubble sub $t2, $s0, $t3 IM lw lw add sw lw add sw $t1, 0($t0) $t2, 4($t0) $t3, $t1, $t2 $t3,12($t0) $t4, 8($t0) $t5, $t1, $t4 $t5, 16($t0) DM Reg lw lw lw add sw add sw Reg $t1, 0($t0) $t2, 4($t0) $t4, 8($t0) $t3, $t1, $t2 $t3,12($t0) $t5, $t1, $t4 $5, 16($t0) 20 Hazardul datelor ȋn execuția pipeline t lw $t1,0($t0) IM lw $t2, 4($t0) DM Reg IM Reg Reg DM add $t3, $t1, $t2 Reg sw $t3, 12($t0) IM lw $t4, 8($t0) add $t5, $t1, $t4 Reg DM Reg DM Reg Reg Reg DM Reg DM Reg Reg Reg DM Reg sw $t5 12($t0) 21 Hazardul datelor ȋn execuția pipeline t lw $t1,0($t0) IM lw $t2, 4($t0) lw $t4, 8($t0) DM Reg IM Reg DM Reg DM Reg add $t3, $t1, $t2 Reg sw $t3, 12($t0) IM add $14, $5, $6 sw $t3, 12($t0) Reg Reg DM Reg DM Reg Reg DM Reg Reg Reg DM Reg 22 Modificarea procesorului pentru eliminarea hazardurilor sub $2, $1,$3 IM and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($t2) DM Reg IM DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg Reg Reg DM Reg 23 Modificarea procesorului pentru eliminarea hazardurilor sub $2, $1,$3 IM and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($t2) DM Reg IM DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg Reg Reg DM Reg 24 Modificarea procesorului pentru eliminarea hazardurilor 1a. 1b. EX/MEM.RegisterRd=ID/EX.RegisterRs EX/MEM.RegisterRd=ID/EX.RegisterRt 2a. 2b. MEM/WB.RegisterRd=ID/EX.RegisterRs MEM/WB.RegisterRd=ID/EX.RegisterRt 25 Modificarea procesorului pentru eliminarea hazardurilor ID/EX EX/MEM Instr[25:21] Registri Data memory Read register 1 Mux Read data 1 Instr[20:16] MEM/WB Read register 2 ALU Address Read data 2 Write register Write data Mux Read data Write data Rs ForwardB Rt Rd 0 ForwardA Rt 1 M u x EX/MEM.registerRd Forwarding unit MEM/WB.registerRd 26 M u x Modificarea procesorului pentru eliminarea hazardurilor EX hazard: IF (EX/MEM.RegWrite and (EX/MEM.registerRd0) and (EX/MEM.RegisterRd=ID/EX.RegisterRs)) ForwardA=10 IF (EX/MEM.RegWrite and (EX/MEM.registerRd0) and (EX/MEM.RegisterRd=ID/EX.RegisterRt)) ForwardB=10 27 Modificarea procesorului pentru eliminarea hazardurilor MEM hazard: IF (MEM/WB.RegWrite and (MEM/WB.registerRd0) and (MEM/WB.RegisterRd=ID/EX.RegisterRs)) ForwardA=01 IF (MEM/WB.RegWrite and (MEM/WB.registerRd0) and (MEM/WB.RegisterRd=ID/EX.RegisterRt)) ForwardB=01 28 Modificarea procesorului pentru eliminarea hazardurilor add $1, $1, $2 add $1, $1, $3 add $1, $1, $4 add $1, $1,$2 add $1, $1, $3 add $1, $1, $4 IM DM Reg IM DM Reg IM Reg Reg Reg DM Reg 29 Modificarea procesorului pentru eliminarea hazardurilor add $1, $1,$2 add $1, $1, $3 add $1, $1, $4 IM DM Reg IM DM Reg IM Reg Reg Reg DM Reg 30 Modificarea procesorului pentru eliminarea hazardurilor IF (MEM/WB.RegWrite and (MEM/WB.registerRd0) and (EX/MEM.RegisterRdID/EX.RegisterRs) and (MEM/WB.RegisterRd=ID/EX.RegisterRs)) ForwardA=01 IF (MEM/WB.RegWrite and (MEM/WB.registerRd0) and (EX/MEM.RegisterRdID/EX.RegisterRt) and (MEM/WB.RegisterRd=ID/EX.RegisterRt)) ForwardB=01 31 Furtul de ciclu t lw $s0, 20($t1) IM DM Reg Reg bubble sub $t2, $s0, $t3 IM Reg DM Reg if (ID/EX.MemRead and ((ID/EX.RegisterRt=IF/ID.RegisterRs) or (ID/EX.Register Rt=IF/ID.RegisterRt))) stall the pipeline 32 Furtul de ciclu lw $2, 20($1) and $4, $2, $5 or $8, $2, $6 add $9, $4, $2 IM DM Reg IM DM Reg IM Reg DM Reg IM Reg Reg Reg DM Reg 33 Furtul de ciclu lw $2, 20($1) and devine nop and $4, $2, $5 or $8, $2, $6 add $9, $4, $2 IM DM Reg IM DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg Reg Reg DM Reg 34 Furtul de ciclu PCWrite Unitate detectie hazard ID/EX W B IF/IDWrite ID/EX. RegisterRt Instr[31:26] M M u x control 0 ALUOp E X AluSrc RegDst Memorie instructiuni PC cod adresa IF/ID 35 Hazardul controlului 40 beq $1, $3, 28 44 and $12, $2, $5 IM DM Reg IM DM Reg IM Reg Reg DM Reg Reg 48 or $13, $6, $2 IM DM Reg Reg 52 add $14, $2, $2 IM 72 lw $4, 50($7) Reg DM Reg Hazardul controlului 40 beq $1, $3, 28 44 and $12, $2, $5 72 lw $4, 50($7) IM DM Reg IM DM Reg IM Reg Reg Reg DM Reg 38