Supplementary notes for pipelining LW SUB BEQ OR ADD ____,____ ____,____,____ ____,____,____ ____,____,____ ____,____,____ ; assume that, condition for branch is not satisfied Prepared by: Cem Ergün Clock Cycle 1 LW before before before before PCSrc EX/MEM ID/EX CONTROL MUX IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX MEM/WB WB ADD Branch ADD RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 REGISTERS DATA MEMORY WRITE DATA ALU CONTROL Sign.
Download ReportTranscript Supplementary notes for pipelining LW SUB BEQ OR ADD ____,____ ____,____,____ ____,____,____ ____,____,____ ____,____,____ ; assume that, condition for branch is not satisfied Prepared by: Cem Ergün Clock Cycle 1 LW before before before before PCSrc EX/MEM ID/EX CONTROL MUX IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX MEM/WB WB ADD Branch ADD RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 REGISTERS DATA MEMORY WRITE DATA ALU CONTROL Sign.
Supplementary notes for pipelining LW SUB BEQ OR ADD ____,____ ____,____,____ ____,____,____ ____,____,____ ____,____,____ ; assume that, condition for branch is not satisfied Prepared by: Cem Ergün Clock Cycle 1 LW before<1> before<2> before<3> before<4> PCSrc EX/MEM ID/EX 0 CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX MEM/WB WB ADD Branch ADD RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 REGISTERS DATA MEMORY WRITE DATA ALU CONTROL Sign Extend 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[20-16] RESULT READ DATA 1 MUX WRITE REGISTER I[15-0] ALU MUX INSTRUCTION MEMORY READ DATA 1 MemToReg ADDRESS MemWrite PC MemRead << 2 0 Clock Cycle 2 SUB LW before<1> before<2> before<3> PCSrc ID/EX 0 CONTROL MUX 1 4 IF/ID EX/MEM RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX MEM/WB WB ADD Branch ADD RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 REGISTERS DATA MEMORY WRITE DATA ALU CONTROL Sign Extend 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[20-16] RESULT READ DATA 1 MUX WRITE REGISTER I[15-0] ALU MUX INSTRUCTION MEMORY READ DATA 1 MemToReg ADDRESS MemWrite PC MemRead << 2 0 Clock Cycle 3 BEQ SUB LW before<1> before<2> PCSrc EX/MEM ID/EX 0 CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX MEM/WB WB ALUSrc ADD Branch ADD RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA ALU CONTROL Sign Extend RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg ADDRESS MemWrite PC MemRead << 2 0 Clock Cycle 4 OR BEQ SUB LW before<1> PCSrc EX/MEM ID/EX 0 CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX WB ALUSrc ADD Branch RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA I[5-0] Sign Extend ALU CONTROL RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg ADDRESS MemWrite PC MemRead << 2 Zero ADD 0 Clock Cycle 5 ADD OR BEQ SUB LW PCSrc EX/MEM ID/EX 0 CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX WB ALUSrc ADD Branch INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA I[5-0] Sign Extend ALU CONTROL RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg ADDRESS MemWrite PC MemRead << 2 Zero ADD RegWrite 0 Clock Cycle 6 after<1> ADD OR BEQ SUB PCSrc EX/MEM ID/EX 0 CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX WB ALUSrc ADD Branch RegWrite INSTRUCTION READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA I[5-0] Sign Extend ALU CONTROL RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg ADDRESS MemWrite PC MemRead << 2 Zero ADD 0 Clock Cycle 7 after<2> after<1> ADD OR EX/MEM ID/EX 0 CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX WB ALUSrc ADD Branch READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA I[5-0] Sign Extend ALU CONTROL RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg INSTRUCTION MemWrite ADDRESS MemRead << 2 Zero ADD RegWrite PC BEQ 0 Clock Cycle 8 after<3> after<2> after<1> CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX WB ALUSrc ADD Branch READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA I[5-0] Sign Extend ALU CONTROL RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg INSTRUCTION MemWrite ADDRESS MemRead << 2 Zero ADD RegWrite PC OR EX/MEM ID/EX 0 ADD 0 Clock Cycle 9 after<4> after<3> after<2> CONTROL MUX 1 4 IF/ID RegWrite MemToReg WB WB Branch MemRead MemWrite M M RegDst ALUOp ALUSrc EX WB ALUSrc ADD Branch READ REGISTER 1 / READ REGISTER 2 ZERO READ DATA 2 0 ALU REGISTERS WRITE REGISTER I[20-16] DATA MEMORY WRITE DATA I[5-0] Sign Extend ALU CONTROL RegDst 0 1 MUX I[15-11] ADDRESS 1 WRITE DATA I[15-0] RESULT ALUOp READ DATA 1 MUX MUX INSTRUCTION MEMORY READ DATA 1 MemToReg INSTRUCTION MemWrite ADDRESS MemRead << 2 Zero ADD RegWrite PC ADD EX/MEM ID/EX 0 after<1> 0