Transcript CSE 331. Computer Organization

Review: Abstract Implementation View

Split memory (Harvard) model - single cycle operation

Simplified to contain only the instructions:



memory-reference instructions: lw, sw
arithmetic-logical instructions: add, sub, and, or, slt
control flow instructions: beq, j
Instruction
Memory
PC

Address
Instruction
Write Data
Register Read
Data
Reg Addr
File
Reg Addr
Read
Data
Reg Addr
Address
ALU
Data
Memory Read Data
Write Data
Sequential components (PC, RegFile, Memory) are edge
triggered

331 Lec 14.1
state elements are written on every clock cycle; if not, need
explicit write control signal
- write occurs only when both the write control is asserted and the
Fall 2002
clock edge occurs
Example

Let’s modify the ISA and remove the ability to
specify an offset for memory access instructions.
Specifically, the load-store instructions would
contain only two registers. In other words, all MIPS
load-store instructions with offsets would become
pseudoinstructions and would be implemented
using two instructions:
lw
$t0, 104($t1)
=>
331 Lec 14.2
Fall 2002
Example cont’d
RegWrite
18
Instruction
17
17
ALU control
overflow
zero
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
MemWrite
Address
ALU
Data
Memory Read Data
Write Data
Data 2
16-bit offset
16
331 Lec 14.3
Sign
Extend
MemRead
32
Fall 2002
Creating a Single Datapath from the Parts

Assemble the datapath segments from the last
lecture, add control lines as needed, and design
the control path

Fetch, decode and execute each instructions in
one clock cycle – single cycle design



no datapath resource can be used more than once per
instruction, so some must be duplicated (e.g., why we
have a separate Instruction Memory and Data Memory)
to share datapath elements between two different
instruction classes will need multiplexors at the input of
the shared elements with control lines to do the selection
Cycle time is determined by length of the longest
path
331 Lec 14.4
Fall 2002
Fetch, R, and Memory Access Portions
Add
RegWrite
ALU control
4
ovf
zero
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Instruction
Memory
PC
MemWrite
Read
Address
Instruction
lw
Write Data
Address
R
ALU
Data
Memory Read Data
Write Data
Data 2
lw / sw
R
Sign
16 Extend
331 Lec 14.5
MemRead
32
Fall 2002
Multiplexor Insertion
Add
RegWrite
ALUSrc ALU control
4
Read
Address
Instruction
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
Address
ALU
Data
Memory Read Data
Write Data
Data 2
Sign
16 Extend
331 Lec 14.6
MemtoReg
ovf
zero
Instruction
Memory
PC
MemWrite
MemRead
32
Fall 2002
Adding the Branch Portion
Branch not taken, R, lw /sw
Add
4
RegWrite
Instruction
Memory
PC
Add
Shift
left 2
Read
Address
Instruction
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
PCSrc
ALUSrc ALU control
ovf
zero
R
ALU
Data
lw
Memory Read Data
Write Data
R
lw / sw
331 Lec 14.7
MemtoReg
Address
Data 2
Sign
16 Extend
MemWrite
MemRead
32
Fall 2002
Adding the Control

Selecting the operations to perform (ALU, Register File and
Memory read/write)

Controlling the flow of data (multiplexor inputs)

Information comes from the 32 bits of the instruction
31

Observations





331 Lec 14.8
R-type: op
25
rs
20
15
rt
rd
10
5
0
shamt funct
op field always
31
25
20
15
in bits 31-26
I-Type: op
address offset
rs
rt
addr of two
registers to be
read are always specified by the
rs and rt fields (bits 25-21 and 20-16)
addr. of register to be written is in one of two places – in rt (bits
20-16) for lw; in rd (bits 15-11) for R-type instructions
base register for lw and sw always in rs (bits 25-21)
offset for beq, lw, and sw always in bits 15-0
Fall 2002
0
(Almost) Complete Single Cycle Datapath
0
Add
4
Add
Shift
left 2
RegDst
RegWrite
1
PCSrc
ALUSrc
MemWrite MemtoReg
ovf
Instruction
Memory
PC
Read
Address
Instr[31-0]
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
MemRead
Instr[5-0]
ALUOp
331 Lec 14.9
Fall 2002
ALU Control

ALU's operation based on instruction type and function
code
331 Lec 14.10
ALU control input
Function
(Binvert + Operation)
000
and
001
or
010
add
110
subtract
111
set on less than
Fall 2002
ALU Control, Con’t

Controlling the ALU makes use of multiple levels of decoding

main control unit generates the ALUOp bits

ALU control unit generates ALU control inputs
Instr op
331 Lec 14.11
funct
ALUOp
desired
action
ALU control
input
lw
xxxxxx
00
sw
xxxxxx
00
beq
xxxxxx
01
add
100000
10
add
010
subt
100010
10
subtract
110
and
100100
10
and
000
or
100101
10
or
001
slt
101010
10
slt
111
Fall 2002
ALU Control Truth Table
F5
F4
F3
F2
F1
F0
ALUOp1
ALUOp0
Op2
Op1
Op0
X
X
X
X
X
X
0
0
0
1
0
X
X
X
X
X
X
X
1
1
1
0
X
X
0
0
0
0
1
X
0
1
0
X
X
0
0
1
0
1
X
1
1
0
X
X
0
1
0
0
1
X
0
0
0
X
X
0
1
0
1
1
X
0
0
1
X
X
1
0
1
0
1
X
1
1
1

Can make use of more don’t cares



since ALUOp does not use the encoding 11
since F5 and F4 are always 10
Logic comes from the K-maps …
331 Lec 14.12
Fall 2002
ALU Control Combinational Logic

From the truth table can design the ALU Control
logic
ALUOp
ALU control block
ALUOp0
ALUOp1
F3
F2
F (5– 0)
Operation2
Operation1
Operation
F1
Operation0
F0
331 Lec 14.13
Fall 2002
(Almost) Complete Datapath with Control Unit
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.14
Fall 2002
R-type Instruction Data/Control Flow
0
Add
ALUOp
Instr[31-26]
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.15
Fall 2002
Store Word Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.16
Fall 2002
Load Word Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
ovf
Instr[25-21]
Instruction
Memory
PC
Read
Address
Instr[31-0]
Read Addr 1
Register Read
Instr[20-16]
Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.17
Fall 2002
Branch Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
ovf
Instr[25-21]
Instruction
Memory
PC
Read
Address
Instr[31-0]
Read Addr 1
Register Read
Instr[20-16]
Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.18
Fall 2002
Main Control Unit
Instr
R-type
RegDst
ALUSrc MemReg
RegWr
MemRd
MemWr
Branch
ALUOp1 ALUOp0
1
0
0
1
X
0
0
1
X
0
1
1
1
1
0
0
0
0
X
1
X
0
X
1
0
0
0
X
0
X
0
X
0
1
X
1
000000
lw
100011
sw
101011
beq
000100
331 Lec 14.19
Fall 2002
Control Unit Logic

From the truth table can design the Main Control
logic
Instr[31]
Instr[30]
Instr[29]
Instr[28]
Instr[27]
Instr[26]
R-type
lw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp0
331 Lec 14.20
Fall 2002
Adding the Jump Operation
Instr[25-0]
Shift
left 2
26
1
28
32
0
PC+4[31-28]
0
Add
Jump
ALUOp
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.21
Fall 2002
Single Cycle Implementation Cycle Time

Unfortunately, though simple, the single cycle
approach is not used because it is inefficient

Clock cycle must have the same length for every
instruction

What is the longest path (slowest instruction)?
331 Lec 14.22
Fall 2002
Instruction Critical Paths
Calculate cycle time assuming negligible delays (for
muxes, control unit, sign extend, PC access, shift left 2,
wires) except:


Instruction and Data Memory (2ns)

ALU and adders (2ns)

Register File access (reads or writes) (1ns)
Instr.
I Mem
Reg Rd
ALU Op
R-type
2
1
2
load
2
1
2
2
store
1
1
2
2
2
beq
2
2
jump
2
331 Lec 14.23
D Mem
Reg Wr
Total
1
6
1
8
7
5
2
Fall 2002
Where We are Headed
Problems with single cycle datapath design



Another approach
Memory
Address
Read Data
(Instr. or Data)
Write Data
331 Lec 14.24
Read Addr 1
Register Read
Read Addr 2Data 1
File
Write Addr
Read
Write Data Data 2
ALU
ALUout
PC

A

use a “smaller” cycle time
have different instructions take different numbers of cycles
a “multicycle” datapath:
B

IR

uses clock cycle inefficiently
and what if we had a more complicated instruction like floating
point multiply?
wasteful of area
MDR

Fall 2002
Complete Datapath
Instr[25-0]
Shift
left 2
26
1
28
32
0
PC+4[31-28]
0
Add
Jump
ALUOp
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.25
Fall 2002
Example I: R instruction
Control
Signal
331 Lec 14.26
Setting
Control
Signal
RegDst
ALUOp1
Jump
AlUOp0
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
Setting
Fall 2002
Example I: lw instruction
Control
Signal
331 Lec 14.27
Setting
Control
Signal
RegDst
ALUOp1
Jump
AlUOp0
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
Setting
Fall 2002
Example I: sw instruction
Control
Signal
331 Lec 14.28
Setting
Control
Signal
RegDst
ALUOp1
Jump
AlUOp0
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
Setting
Fall 2002
Example I: beq instruction
Control
Signal
331 Lec 14.29
Setting
Control
Signal
RegDst
ALUOp1
Jump
AlUOp0
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
Setting
Fall 2002
Example II: cycle length
Calculate cycle time assuming negligible
delays (for muxes, control unit, sign extend,
PC access, shift left 2, wires) except:


Instruction and Data Memory (2ns)

ALU (2ns)

Register File access (reads or writes) (1ns)
Adder
for PC+4 (5ns)
Adder
for branch address computation (5ns)
331 Lec 14.30
Fall 2002
Example III:

Describe the effect that a single stuck-at-0 fault
(I.e., regardless of what it should be, the signal is
always 0) would have on the multiplexors in the
single-cycle datapath. Which instruction, if any,
would still work? Consider each of the following
faults separately: RegDst = 0, ALUSrc = 0,
MemtoReg = 0, Zero = 0;
331 Lec 14.31
Fall 2002
Example IV:

We wish to add the instruction addi to the singlecycle datapath. Add any necessary datapaths and
control signals.
Control
Signal
RegDst
Setting
Control
Signal
ALUOp1
Jump
AlUOp0
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
331 Lec 14.32
Setting
Fall 2002
Complete Datapath
Instr[25-0]
Shift
left 2
26
1
28
32
0
PC+4[31-28]
0
Add
Jump
ALUOp
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
331 Lec 14.33
Fall 2002
Example V: add jal
Instr[25-0]
Shift
left 2
26
1
28
32
0
PC+4[31-28]
0
Add
Jump
ALUOp
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegDst1
RegDst
Instr[25-21]
PC
RegWrite
ovf
Read Addr 1
Instruction
Register Read
Memory
Instr[20-16] Read Addr 2 Data 1
Instr[31-0]
Read
File
0
Address
Write
Addr
31
Read
1
Write Data
zero
ALU
0
Address
Data
Memory
1
Read Data
Write Data
Data 2
1
Instr[15
-11]
Instr[15-0]
MemtoReg1
Sign
16 Extend
32
0
ALU
control
Instr[5-0]
331 Lec 14.34
1
Fall 2002
0
Example V: add jal (cont’d)
Control
Signal
RegDst
Setting
Control
Signal
ALUOp1
Jump
AlUOp0
Branch
MemWrite
MemRead
ALUSrc
MemtoReg
RegWrite
MemtoReg1
RegDst1
331 Lec 14.35
Setting
Fall 2002