Transcript CS 230 Chapter 3 Arithmetic for Computers

CS 230: Computer Organization
and Assembly Language
Aviral Shrivastava
Department of Computer Science and Engineering
School of Computing and Informatics
Arizona State University
Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary
Jane Irwin, PSU, Ande Carle, UCB
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Announcements
• Project 3
– MIPS Assembler
• Midterm Reviews
• Quiz 4
– Nov 5, 2009
– Single-cycle implementation
• Finals
– Tuesday, Dec 08, 2009
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What is this?
00100111101111011111111111100000
10101111101111110000000000010100
10101111101001000000000000100000
10101111101001010000000000100100
10101111101000000000000000011000
10101111101000000000000000011100
10001111101011100000000000011100
10001111101110000000000000011000
00000001110011100000000000011001
00100101110010000000000000000001
00101001000000010000000001100101
10101111101010000000000000011100
00000000000000000111100000010010
00000011000011111100100000100001
00010100001000001111111111110111
10101111101110010000000000011000
00111100000001000001000000000000
10001111101001010000000000011000
00001100000100000000000011101100
00100100100001000000010000110000
10001111101111110000000000010100
00100111101111010000000000100000
00000011111000000000000000001000
00000000000000000001000000100001
int main (int argc, char *argv[])
{
int i;
int sum = 0;
for (i = 0; i <= 100; i = i + 1) sum = sum + i * i;
printf ("The sum from 0 .. 100 is %d\n", sum);
}
MIPS machine language code for a routine
to compute and print the sum of the
squares of integers between 0 and 100.
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Abstract Implementation View
• Two types of functional units:
– elements that operate on data values (combinational)
– elements that contain state (sequential)
Instruction
Memory
PC
Address
Instruction
Write Data
Register Read
Data
Reg Addr
File
Reg Addr
Read
Data
Reg Addr
Address
ALU
Data
Memory Read Data
Write Data
• Single cycle operation
• Split memory (Harvard) model - one memory for instructions and
one for data
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Fetching Instructions
• Fetching instructions involves
– reading the instruction from the Instruction Memory
– updating the PC to hold the address of the next instruction
Add
4
Instruction
Memory
PC
Read
Address
Instruction
– PC is updated every cycle, so it does not need an explicit write control
signal
– Instruction Memory is read every cycle, so it doesn’t need an explicit
read control signal
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Executing R Format Operations
• R format operations (add, sub, slt, and, or)
31
R-type: op
25
rs
20
15
10
rt
rd
5
0
shamt funct
– perform the indicated (by op and funct) operation on values in rs and rt
– store the result back into the Register File (into location rd)
RegWrite
Instruction
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
ALU control
ALU
overflow
zero
Data 2
– Note that Register File is not written every cycle (e.g. sw), so we need an
explicit write control signal for the Register File
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Load and Store Operations
RegWrite
Instruction
ALU control
overflow
zero
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
16
Address
ALU
Data
Memory Read Data
Write Data
Data 2
Sign
Extend
MemWrite
MemRead
32
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Executing Branch Operations
Add
4
Add
Shift
left 2
Branch
target
address
ALU control
PC
Read Addr 1
Instruction
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
16
zero (to branch
control logic)
ALU
Data 2
Sign
Extend
32
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Executing Jump Operations
• Jump operations have to
31
25
0
J-Type: op
jump target address
– replace the lower 28 bits of the PC with the lower 26 bits of
the fetched instruction shifted left by 2 bits
Add
4
4
Instruction
Memory
PC
Read
Address
Shift
left 2
Jump
address
28
Instruction
26
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Adding the Pieces Together
Add
RegWrite
ALUSrc ALU control
4
MemtoReg
ovf
zero
Instruction
Memory
PC
MemWrite
Read
Address
Instruction
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
Address
ALU
Write Data
Data 2
Sign
16 Extend
Data
Memory Read Data
MemRead
32
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Adding the Branch Portion
Add
4
Shift
left 2
RegWrite
Instruction
Memory
PC
Read
Address
Instruction
MemWrite
MemtoReg
Address
ALU
Data
Memory Read Data
Write Data
Data 2
Sign
16 Extend
PCSrc
ALUSrc ALU control
ovf
zero
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
Add
MemRead
32
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Adding the Jump Portion
26
Shift
left 2
Jump
32
28
1
PC+4[31-28]
0
Add
4
Shift
left 2
RegWrite
Instruction
Memory
PC
Read
Address
Instruction
MemWrite
MemtoReg
Address
ALU
Data
Memory Read Data
Write Data
Data 2
Sign
16 Extend
PCSrc
ALUSrc ALU control
ovf
zero
Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data
Add
MemRead
32
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MIPS Machine (with Controls)
Instr[25-0]
Shift
left 2
26
1
28
32
0
PC+4[31-28]
0
Add
Jump
ALUOp
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
Instr[5-0]
ALU
control
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ALU Control

ALU's operation based on instruction type and function code
operation
a
32
ALU
32
b
32
result
ALU control input
Function
000
and
001
or
010
add
110
subtract
111
set on less than
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ALU Control
• Controlling the ALU makes use of multiple levels of decoding
– main control unit generates the ALUOp bits
– ALU control unit generates ALU control inputs
Instr op
opcode
funct
ALUOp desired
action
ALU control
input
lw
23
xxxxxx
00
add
010
sw
2b
xxxxxx
00
add
010
beq
4
xxxxxx
01
subtract
110
add
0
100000
10
add
010
subt
0
100010
10
subtract
110
and
0
100100
10
and
000
or
0
100101
10
or
001
slt
0
101010
10
slt
111
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ALU Control Truth Table
F5
F4
F3
F2
F1
F0
ALUOp1
ALUOp0
Op2
Op1
Op0
X
X
X
X
X
X
0
0
0
1
0
X
X
X
X
X
X
X
1
1
1
0
X
X
0
0
0
0
1
0
1
0
X
X
0
0
1
0
1
1
1
0
X
X
0
1
0
0
1
0
0
0
X
X
0
1
0
1
1
0
0
1
X
X
1
0
1
0
1
X
X
X
X
X
1
1
1
• Can make use of more don’t cares
– since ALUOp does not use the encoding 11
– since F5 and F4 are always 10
• Logic comes from the K-maps …
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ALU Control Combinational Logic
• From the truth table can design the ALU Control logic
ALUOp
ALU control block
ALUOp0
ALUOp1
F3
F2
F (5– 0)
Operation2
Operation1
Operation
F1
Operation0
F0
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Datapath with Control Unit
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
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Main Control Unit
Instr
RegDst
ALUSrc
MemtoReg RegWr MemRd MemWr
Branch
ALUOp1 ALUOp2
R-type
000000
lw
100011
sw
101011
beq
000100

Completely determined by the instruction opcode field
l
Note that a multiplexor whose control input is 0 has a definite
action, even if it is not used in performing the operation
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R-type Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
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Main Control Unit
Instr
R-type
RegDst
ALUSrc
1
0
MemtoReg RegWr
0
1
MemRd
MemWr
Branch
X
0
0
ALUOp1 ALUOp0
1
X
000000
lw
100011
sw
101011
beq
000100
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Load Word Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
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Main Control Unit
Instr
R-type
RegDst
ALUSrc
MemtoReg RegWr
1
0
0
0
1
1
MemRd
MemWr
Branch
ALUOp1 ALUOp0
1
X
0
0
1
X
1
1
0
0
0
0
000000
lw
100011
sw
101011
beq
000100
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Store Word Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
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Main Control Unit
Instr
R-type
RegDst
ALUSrc
MemtoReg RegWr
MemRd
MemWr
Branch
1
0
0
0
1
X
1
ALUOp1 ALUOp0
1
X
0
0
1
X
1
1
1
0
0
0
0
X
0
X
1
0
0
0
000000
lw
100011
sw
101011
beq
000100
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Branch Instruction Data/Control Flow
0
Add
Add
Shift
left 2
4
ALUOp
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
ALU
control
Instr[5-0]
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Main Control Unit
Instr
R-type
RegDst
ALUSrc
MemtoReg RegWr
MemRd
MemWr
Branch
1
0
0
0
1
X
X
ALUOp1 ALUOp0
1
X
0
0
1
X
1
1
1
0
0
0
0
1
X
0
X
1
0
0
0
0
X
0
X
0
1
X
1
000000
lw
100011
sw
101011
beq
000100
• Completely determined by the instruction opcode field
– Note that a multiplexor whose control input is 0 has a definite action,
even if it is not used in performing the operation
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Control Unit Logic
• From the truth table can design the Main Control logic
Instr[31]
Instr[30]
Instr[29]
Instr[28]
Instr[27]
Instr[26]
R-type
lw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
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ALUOp0
Complete Datapath with Controls
Instr[25-0]
Shift
left 2
26
1
28
32
0
PC+4[31-28]
0
Add
Jump
ALUOp
Add
Shift
left 2
4
1
PCSrc
Branch
MemRead
MemtoReg
MemWrite
Instr[31-26] Control
Unit
ALUSrc
RegWrite
RegDst
Instruction
Memory
PC
Read
Address
Instr[31-0]
ovf
Instr[25-21] Read Addr 1
Register Read
Instr[20-16] Read Addr 2 Data 1
File
0
Write Addr
Read
1
Instr[15
-11]
Instr[15-0]
Write Data
zero
ALU
Address
Data
Memory Read Data
1
Write Data
0
0
Data 2
1
Sign
16 Extend
32
Instr[5-0]
ALU
control
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Disadvantages of Single Cycle Implementation
• Uses the clock cycle inefficiently – the clock cycle
must be timed to accommodate the slowest
instruction
– especially problematic for more complex instructions
like floating point multiply
• Is wasteful of area since some functional units
must be duplicated since they can not be “shared”
during an instruction execution
– e.g., need separate adders to do PC update and branch
target address calculations, as well as an ALU to do Rtype arithmetic/logic operations and data memory
address calculations
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Yoda says…
Use your feelings, Obi-Wan, and find him you will
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