Princess Sumaya Univ. Computer Engineering Dept. Chapter 2: Princess Sumaya University 22444 – Computer Arch.
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Transcript Princess Sumaya Univ. Computer Engineering Dept. Chapter 2: Princess Sumaya University 22444 – Computer Arch.
Princess Sumaya Univ.
Computer Engineering Dept.
Chapter 2:
Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Basic Computer Organization
The 5 Classic Components of a Computer
The Basic Hardware/Software Interface
The Stored-Program Concept
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Instructions
Assembly Language Instruction:
Perform:
a=b+c
ADD a, b, c
;ab+c
What are ‘a’, ‘b’ and ‘c’?
● The storage concept:
♦ Registers (R1, R2 …)
♦ Memory
Sequence of Instructions:
Perform:
a = (b + c) – (d + e)
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Memory Operands
Data Transfer Instructions
● Memory Address (Location)
● Slower than registers
● Lower bandwidth than registers
Memory
0
1
2
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•
Load and Store Instructions
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22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Constant Operands
Memory Operand
Perform a = b + 4
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21
Memory
22
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4
b
Immediate Operand
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Memory Access
8 bit
Memory
1 KB
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21
4 KB
22
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01
Address & Data
43
1024
Height and Width
1 KB
16 Locations
1 K Locations
1 M Locations
Read & Write
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Stored Program Architecture
Memory
1024 x 32
Instructions
(Program)
Opcode
Operands
Operands
(Data)
Binary Operand
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22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Memory Organization
Byte Access
Word Access
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20 Byte
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20 Byte Byte
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20 Byte Byte Byte Byte
21 Byte
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22 Byte Byte
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24 Byte Byte Byte Byte
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Memory Organization
Mixed Access
● Little Endian
● Odd/Even
Alignment
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20 Byte Byte
22 Byte Byte
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MSB
DATA
BUS
LSB
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Memory Organization
Mixed Access
● Alignment!
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20 Byte Byte Byte Byte
24 Byte Byte Byte Byte
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MSB
DATA
BUS
LSB
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Computer Engineering Dept.
Instruction Representation
Instruction Format
Opcode
Operands
Assembly
Language
ADD R1, R2,
0101 0001 0010
5
1
Machine Language & Machine Code
47
00101111
2
2F
5122F
Machine
Language
Sequence of instructions
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Operations (Opcodes)
Arithmetic
1 0 1 0 0 1 1 1
● Add, Sub, Mul, Div, Inc, Dec …
Logic
1 0 1 0 0 1 1 1
● Shift
♦ Logical & Arithmetic
♦ Right & Left
● Bitwise AND, OR, XOR
● Complement (NOT)
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Princess Sumaya University
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Operations (Opcodes)
Shift Operation for Multiplication
● Multiply by 2
0 0 0 0 0 1 0 0
♦ Shift Left 1 bit
♦ Unsigned Binary
♦ 2’s Complement
1 1 1 1 1 1 0 1
● Multiply by 10
♦ BCD
0000 0100 1001
♦ Shift Left 4 bits
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Control Instructions
Making Decisions (Conditional Branches)
Perform if (i == j) then a = b + c else a = b – c
i == j ?
a=b+c
a=b–c
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Computer Engineering Dept.
Control Instructions
Transferring Execution
● Unconditional Branch or Jump
● Call Subroutine
● Software Interrupt
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Computer Engineering Dept.
RISC & CISC
Reduced Instruction Set Computer
● 32-Bit Storage:
♦ Registers (R1, R2 … R31)
♦ Memory
● Arithmetic operations:
♦ Simple
♦ Limited to registers
Complicated Instruction Set Computer
● IA-32
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Computer Engineering Dept.
Intel Architecture IA-32
General-Purpose Registers (GPRs)
Also:
“Accumulator”
EAX
EAX AX AX
AL
“Base”
EBX
BX
BL
“Count”
ECX
CX
CL
“Division”
EDX
DX
DL
“String Source”
ESI
SI
“String Destination”
EDI
DI
Segment Registers
CS
Segmented Memory Addressing
(Real Mode)
SS
DS
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22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Intel Architecture IA-32
Variable Length Instruction Format
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Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Intel Architecture IA-32
Year
Microprocessor
Address Bits
Data Bits
Transistors
1971
4004
12
4
2,300
1974
8080
16
8
6,000
1978
8086
20
16/8
29,000
1982
80286
24
16/8
134,000
1985
80386
32
32/16/8
275,000
1989
80486
32
32/16/8
1,200,000
1992
Pentium
32
32/16/8
3,100,000
1995
Pentium Pro
32
32/16/8
5,500,000
1997
Pentium II
32
32/16/8
7,500,000
1999
Pentium III
32
32/16/8
9,500,000
2001
Pentium 4
32
32/16/8
42,000,000
2004
Pentium 4 EM64T
64
32/16/8
125,000,000
2008
Core 2 Quad
64
32/16/8
820,000,000
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Princess Sumaya University
Chapter 2
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Chapter 2 Exercise 1
Write an assembly language program to perform
a+2b where ‘a’ and ‘b’ are stored in R1 and R2.
Write an assembly language program to swap two
locations at memory addresses 10 and 20.
Rewrite the following program to run faster:
SUB R1, R1, R1
INC R1
ADD R2, R3, R1
A memory has 4 bits of address and 4 bits of data.
Determine the total number of bits inside it.
Princess Sumaya University
22444 – Computer Arch. & Org. (1)
Computer Engineering Dept.
Chapter 2 Exercise 2
Determine the value of R1:
LD R1, M [ 43 ]
Write the assembly
instruction at 44.
40 00100011010001010000000100010000
44 10110001000110100001001000010001
Opcode
Operand 1
Operand 2
Operand 3
Add (= B1) Reg (5 bits) Reg (5 bits) Reg (5 bits)
Add (= B2) Reg (5 bits) Reg (5 bits)
Constant
Assuming 8-bit registers, determine the value of R1:
Load Immediate R1, Binary ‘11110010’
Arith Shift Right R1
Assuming i and j are integers, R1= i and R2 = j, write the Clanguage statement for:
Compare
R1, R2
Jump Equal Label_1
Clear
R1
Label_1: Clear
R2