Transcript UP2 Education Board

Quick Start to VHDL
VHDL
Very Hard Difficult Language
!!!!!!!
Quick Start to VHDL
VHDL
Very High Speed Integrated Circuits
Hardware Description Language
How You can do VHDL
1.Behavior Method
Specify the relationship between inputs
and output
Y<= (A XOR B) OR C
2. Structural Method
Mapping between
logical components
VHDL Fundamentals
–Libraries and Packages
–Entity (Data Types)
–Architecture
–Signals (Data Types)
–Operators
Libraries and Packages
 Libraries provide a set components and functions
that simplify the task of designing
 Packages provide subprograms maybe used in a
design
 The following is an example of the use of the IEEE
library and its STD_LOGIC_1164 package:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Entities
 An entity is a specification of the design’s external interface
 Entity declarations specify the following:
1. Name of the entity
2. Set of port declarations defining the inputs and outputs to the
hardware design
 The following is an example of an entity declaration:
Port Direction
ENTITY orgate IS
PORT (
a : IN
STD_LOGIC;
b : IN
STD_LOGIC;
y : OUT
STD_LOGIC );
END orgate;
Port Data Type
Ports

Port name choices:
– Always begin with a letter
– Case insensitive

Port direction choices:
IN
OUT

Input port
Output port
Port signal type (suggested) choices:
– STD_LOGIC
– STD_LOGIC_VECTOR(<max> DOWNTO <min>)
for 8bit data type : std_logic_vector(7 downto 0)
– Integer
– Real
– Boolean
Architectures
 An architecture is a specification of the design’s
internal implementation
 The following is an example of an architecture
declaration:
ARCHITECTURE a OF orgate IS
BEGIN
y <= a or b;
END a;
Logical Operators
 VHDL supports the following logical operators:
 AND
 OR
 XOR
 XNOR
 NOT
 NAND
 NOR
Other Operators
 VHDL supports the following relational operators:
=
/=
<
>
(Equal)
(Not Equal)
(Less Than)
(Greater Than)
 VHDL supports the following mathematical operators:
+
*
/
Abs
**
(Addition)
(Subtraction)
(Multiplication)
(Division)
(Absolute)
(Exponentiation)
Complete Example
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY orgate IS
PORT (
a : IN
STD_LOGIC;
b : IN
STD_LOGIC;
y : OUT
STD_LOGIC );
END orgate;
ARCHITECTURE a OF orgate IS
BEGIN
y <= a or b;
END a;
Start With MaxPlus II
 Software is used to check, compile and
simulate the VHDL code.
 start MAX+PLUS II
Start With MaxPlus II
 Select File  New.
 Select Text Editor File.
Start With MaxPlus II
 In the new empty window write the VHDL input file.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL
ENTITY orgate IS
PORT (
a : IN
STD_LOGIC;
b : IN
STD_LOGIC;
c : OUT
STD_LOGIC );
END orgate;
ARCHITECTURE a OF orgate IS
BEGIN
c <= a or b;
END a;
Start With MaxPlus II
 Save the File as Vhd ,Select File  Save As.
Save using the same name of the entity
Start With MaxPlus II
 Set project to Current File ,Select File
Project  Set Project to Current File.
Start With MaxPlus II
 Compile by selecting File  Project  Save and
Compile.
A window with the modular compiler,
will monitor compiling, warnings and
errors.
Start With MaxPlus II
 For simulation:
 Choose File  New, select Waveform Editor File,
and then click OK
 Select Node  Enter Node from SNF
 Click on List to list the input & output ports
 Select these ports
Start With MaxPlus II
 Modify the inputs
 Select File  Project  Save and
Simulate
2nd Complete
library ieee;
use ieee.std_logic_1164.all;
--full_adder
entity full_adder is
port ( a,b,cin: in std_logic;
sum,cout:out std_logic);
end full_adder;
architecture full_adderfun of full_adder is
signal sum1, c1, c2:std_logic;
begin
sum1 <= a xor b;
sum <= sum1 xor cin;
c1 <= sum1 and cin;
c2 <= a and b;
cout <= c1 or c2;
end full_adderfun;
Example
Signals
 Signals represent wires and storage
elements within a VHDL design
 Signals only be defined inside architectures
 Signals are associated with a data type
UP2 Education Board
The board contains:
•FLEX® 10K FPGA device
•MAX® 7000 PLD
•One Oscillator
•Four Jumpers
•Four Push Button
•16 LED’S
•Four Seven Segment Displays
•Three Switches
•Four Expansions
UP2 Education Board
FLEX® 10K FPGA
•
Contains 70,000 gates, 3744 logic elements,
4096 register and 18432 RAM bits.
•
Connections are made using pass-transistors,
transmission gates, or multiplexers
•
Fast in-circuit reconfiguration
•
Volatile memory chip
UP2 Education Board
MAX® 7000 PLD
•
EPROM (Erasable Programmable) Technology
•
Non-volatile memory chip
•
Capacity of 2,500 gates and 128 macro cells
•
Each macro cell has a programmable-AND/fixed-OR
array as well as a configurable register
UP2 Education Board
Oscillator
 The UP Education Board contains a
25.175-MHz crystal oscillator.
 The output of the oscillator drives a clock input
to the
EPM7128S device (pin 83)
FLEX 10K device (pin 91)
UP2 Education Board
Jumpers
 The UP Education Board has four three-pin jumpers
(TDI, TDO, DEVICE, and BOARD)

 The jumpers setting to configure:
FLEX 10K
EPM7128S
UP2 Education Board
Push Buttons
 Four push buttons: Two are connected to EPM7128S
(MAX_PB1 & MAX_PB2 ) and two are connected to
FLEX 10K (FLEX_PB1 & FLEX_PB2 )
 Each push button is pulled-up to 5 V through a 10-KΩ
resistor. (Active Low when pressed)
 MAX_PB1 & MAX_PB2 can be connected to any input
of the device expansion.
 FLEX_PB1 connected to pin 28, and FLEX_PB2
connected to pin 29.
UP2 Education Board
LED’s
 Contains 16 LEDs that are pulled-up with a 330Ω resistor.
 An LED is illuminated when a logic 0 is applied
to the female header associated with the LED
UP2 Education Board
7 Segment Display
 Four 7 Segment Displays: Two are connected to
EPM7128S and two to FLEX 10K
 Each LED segment of the display can be
illuminated by driving the connected pin with a
logic 0
UP2 Education Board
7 Segment Display
FLEX 10K
EPM7128S
UP2 Education Board
Switches
 Three 8 switches: Two are connected to EPM7128S
(MAX_SW1 & MAX_SW2 Switches) and one to
FLEX 10K (FLEX_SW1 Switches)
 An input pin is set to logic 1 when the switch is open
and set to logic 0 when the switch is closed.
 MAX_SW1 & MAX_SW2 Switches can be connected
to any input of the device expansion
 FLEX_SW1 Switches are connected as following:
UP2 Education Board
Switches
UP2 Education Board
Expansions
 MAX_EXPANSION FLEX_EXPAN_A,
FLEX_EXPAN_B, and FLEX_EXPAN_C are
dual rows of 0.1-inch spaced holes for accessing
signal I/O pins
UP2 Education Board
Expansions
UP2 Education Board
Expansions
UP2 Education Board
Expansions
UP2 Education Board
Expansions
Programming With MaxPlus II
 Select Assign  Device
 To assign the chip that will be used to configure
the design. Here FLEX10K is assigned with the
chip number EPF10K70RC240-2 that is written on
the chip.
Programming With MaxPlus II
 Select Assign  Pin/Location/Chip
Click List
Click Search
Programming With MaxPlus II
Pin 28 is Flex_PB1
Pin 29 is Flex_PB2
Pin 41 is Flex switch1
Pin 6 is (a) of 7seg1
Pin 17 is (a) of 7seg2
Programming With MaxPlus II
 Select Mxx+Pluss II Programmer
 Select JTAG  Multi-device JTAG chain so that a checkmark
appears to the left of the option.
 Hit the Select programming File button and select full_adder.sof.
 Click OK, then click the ADD button and the new filename should move
into the list in the inner window.
 Select the Detect JTAG Chain Info button. The system should
respond with “JTAG chain information confirmed by hardware check”.
 If not, double check cables, power, jumpers, and make sure you have
the correct file name and chip listed in the inner window.
 Click OK to exit the JTAG Multi-device Setup window.
Programming With MaxPlus II
 The configure button in the programming window should
now be highlighted.
 Click on the configure button to download to the board.
 Just a few seconds are required to download. If download
is successful, a window with Configuration Complete is
displayed - click OK.
 If the configure button is not highlighted, try Option 
Hardware Setup from the pull-down window. confirm the
port settings and click OK. Also confirm that the JTAG
setup dialog information is correct. If you still have
problems confirm that the printer port BIOS settings ESP or
EPP mode.