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Graduate Institute of Electronics Engineering, NTU Course Introduction Lecturer： 吳安宇 Date：2004/02/20 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Contexts Digital system design plays an important role in implementing digital functions in modern system-on-chip (SOC) design. In this course, we will focus on developing the design skills for undergraduate students so that they can be familiar with state-of-theart digital front-end design skills and flow. 2004/02/20 吳安宇 教授 pp. 2 Graduate Institute of Electronics Engineering, NTU This course covers: Firstly, we will introduce the Hardware Description Language (HDL). The chosen HDL is Verilog. We will formally cover The HDL grammar The coding guideline The synthesis guideline Modern cell-based synthesis flow Reuse Manual Methodology (RMM) 2004/02/20 吳安宇 教授 pp. 3 Graduate Institute of Electronics Engineering, NTU This course covers: Secondly, we will ask students to design an advanced MIPS CPU. It is based on the knowledge of “Computer Organization and Design.” The assignment covers Instruction development. HDL coding and simulation of major blocks such as Arithmetic Logic Unit (ALU) and Control Unit (CU). Enhanced CPU design with Pipelining and Forwarding Integration of whole design. Thirdly, port the MIPS CPU design to FPGA board and perform emulation (optional) 2004/02/20 吳安宇 教授 pp. 4 Graduate Institute of Electronics Engineering, NTU Course Outline Week Course Speaker Note 1st (2/20) Overview DSD Course Prof. Wu Introduction 2nd (2/27) Overview of Verilog HDL 3rd (3/5) Modeling and Verification 4th (3/12) Overview of MIPS CPU Architecture 5th (3/19) Behavior Models 6th (3/26) Synthesis of Combinational Circuits 彈性放假 (6/14 補課) Behavior Model of MIPS CPU Architecture 期中考 Lab2 期中考週 7th (4/2) 8th (4/9) th 9 (4/16) Lab1 10th (4/23) Synthesis of Sequential Circuits 11th (4/30) State machines & Datapath Controllers 12th (5/7) RTL Coding of MIPS CPU Architecture Lab3 th 13 (5/14) From single module to complex design 14th (5/21) Improving Timing, Area, and Power 15th (5/28) Program MIPS CPU th 16 (6/4) Lab4 Coding Style th 17 (6/11) Industry Design Guidelines 18th (6/14) Final project report 1 18th (6/18) Final project report 2 2004/02/20 期末考週 吳安宇 教授 pp. 5 Graduate Institute of Electronics Engineering, NTU Verilog HDL Outlines Overview of Verilog Hardware Describe Languages Modeling and Verification with Verilog-HDLs Logic Design with Behavior Models Introduction to synthesis with Verilog-HDLs Synthesis of Combinational Circuits Synthesis of Sequential Circuits State machines & Datapath Controllers Architecture and Algorithm Coding Style 2004/02/20 吳安宇 教授 pp. 6 Graduate Institute of Electronics Engineering, NTU Advanced MIPS CPU Outlines Overview of MIPS CPU Architecture Instruction Sets Arithmetic Logic Unit Design Control Flow Design Pipelining Architecture Forwarding Architecture 2004/02/20 吳安宇 教授 pp. 7 Graduate Institute of Electronics Engineering, NTU Course Information Instructor: 許槐益(Huai-Yi Hsu) E-mail: [email protected] Office: Rm. E2-331, New E.E. Building Text Book “Adanced Digital Design with the Verilog HDL.” by Michael D. Ciletti, Prentice Hall, 2003 Reference Book “Verilog Styles for Synthesis of Digital Systems,” by David R. Smith and Paul D. Franzon, Prentice Hall, 2001 (全華代理) 2004/02/20 吳安宇 教授 pp. 8 Graduate Institute of Electronics Engineering, NTU Reference Books M. D. Ciletti, “Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL,” Prentice-Hall, 1999. “Verilog HDL: A Guide to Digital Design and Synthesis,” 2nd ed., by Samir Palnitkar, SunSoft, 2003 (全華代理) “Reuse Methodology Manual for System-On-A-Chip Designs,” 3rd Edition, by Michael Keating, Pierre Bricaud, Kluwer Academic Publishers, 2002. “Computer organization & design: The hardware/software interface,” 2nd edition, by David A. Patterson and John L. Hennessy, Morgan Kaufmann, 1998. 黃英叡、江文啓、黃稚存、張銓淵編譯, “Verilog硬體描述語言,” 全華書局, 2001. 楊紹聖、蕭鳴均、李進福、蔡培元編譯, “Verilog數位電腦設計,” 全華書局, 2001. 2004/02/20 吳安宇 教授 pp. 9 Graduate Institute of Electronics Engineering, NTU Course Grading Participation 2% (about four times). One mid-terms 22% Final Projects (demo and presentation) 36% Computer Labs and Homework (about four labs and ten homework) 40% 2004/02/20 吳安宇 教授 pp. 10 Graduate Institute of Electronics Engineering, NTU Background Programming Language, Logic Design (basic) Computer Organization and Design (required) VLSI Design (optional) 2004/02/20 吳安宇 教授 pp. 11