Transcript Document

EE207: Digital Systems I,
Semester I 2003/2004
CHAPTER 3 -ii:
Combinational Logic Design –
Design Procedure, Encoders/Decoders
(Sections 3.4 – 3.6)
Overview
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Design Procedure
Code Converters
Binary Decoders
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Expansion
Circuit implementation
Binary Encoders
Priority Encoders
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Combinational Circuit Design
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Design of a combinational circuit is the
development of a circuit from a
description of its function.
Starts with a problem specification and
produces a logic diagram or set of
boolean equations that represent the
circuit.
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Design Procedure
1.
2.
3.
4.
5.
Determine the required number of inputs
and outputs and assign variables to them.
Derive the truth table that defines the
required relationship between inputs and
outputs.
Obtain and simplify the Boolean function (Kmaps, algebraic manipulation, CAD tools, …).
Consider any design constraints (area, delay,
power, available libraries, etc).
Draw the logic diagram.
Verify the correctness of the design.
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Design Example
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Design a combinational circuit with 4
inputs that generates a 1 when the # of
1s equals the # of 0s. Use only 2-input
NOR gates
…
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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More Examples - Code Converters
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Code Converters transform/convert
information from one code to another:
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BCD-to-Excess-3 Code Converter
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BCD-to-Seven-Segment Converter
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Useful in some cases for digital arithmetic
Used to display numeric info on 7 segment
displays
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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BCD-to-Excess-3 Code Converter
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Design a circuit that converts a binarycoded-decimal (BCD) codeword to its
corresponding excess-3 codeword.
Excess-3 code: Given a decimal digit n, its
corresponding excess-3 codeword (n+3)2
Example:
n=5  n+3=8  1000excess-3
n=0  n+3=3  0011excess-3
We need 4 input variables (A,B,C,D) and 4
output functions W(A,B,C,D), X(A,B,C,D),
Y(A,B,C,D), and Z(A,B,C,D).
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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BCD-to-Excess-3 Converter (cont.)
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The truth table relating the input and output variables is shown below.
Note that the outputs for inputs 1010 through 1111 are don't cares (not
shown here).
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Maps for BCD-to-Excess-3 Code Converter
The K-maps for are constructed using the don't care terms
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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BCD-to-Excess-3 Converter (cont.)
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Another Code Converter Example:
BCD-to-Seven-Segment Converter
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Seven-segment display:
7 LEDs (light emitting diodes), each one
controlled by an input
a
 1 means “on”, 0 means “off”
f
b
 Display digit “3”?
g
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Set a, b, c, d, g to 1
 Set e, f to 0
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e
c
d
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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BCD-to-Seven-Segment Converter
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Input is a 4-bit BCD code  4 inputs (w,
x, y, z).
Output is a 7-bit code (a,b,c,d,e,f,g) that
allows for the decimal equivalent to be
displayed.
a
Example:
f
Input: 0000BCD
 Output: 1111110
(a=b=c=d=e=f=1, g=0)
g
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e
b
c
d
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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BCD-to-Seven-Segment (cont.)
Truth Table
Digit
0
1
2
3
4
5
6
7
wxyz
0000
0001
0010
0011
0100
0101
0110
0111
abcdefg
1111110
0110000
1101101
1111001
0110011
1011011
X011111
11100X0
Digit
8
9
wxyz
1000
1001
1010
1011
abcdefg
1111111
111X011
XXXXXXX
XXXXXXX
1100
1101
1110
XXXXXXX
XXXXXXX
XXXXXXX
1111
XXXXXXX
??
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Decoders
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A combinational circuit that converts
binary information from n coded inputs
to a maximum 2n decoded outputs
 n-to- 2n decoder
n-to-m decoder, m ≤ 2n
Examples: BCD-to-7-segment decoder,
where n=4 and m=7
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Decoders (cont.)
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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2-to-4 Decoder
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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2-to-4 Active Low Decoder
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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3-to-8 Decoder
data
address
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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3-to-8 Decoder (cont.)
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Three inputs, A0, A1, A2, are decoded into
eight outputs, D0 through D7
Each output Di represents one of the
minterms of the 3 input variables.
Di = 1 when the binary number A2A1A0 = i
Shorthand: Di = mi
The output variables are mutually exclusive;
exactly one output has the value 1 at any time,
and the other seven are 0.
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Implementing Boolean functions
using decoders
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Any combinational circuit can be constructed
using decoders and OR gates! Why?
Here is an example:
Implement a full adder circuit with a decoder
and two OR gates.
Recall full adder equations, and let X, Y, and Z
be the inputs:
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S(X,Y,Z) = X+Y+Z = m(1,2,4,7)
C (X,Y,Z) = m(3, 5, 6, 7).
Since there are 3 inputs and a total of 8
minterms, we need a 3-to-8 decoder.
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Implementing a Binary Adder
Using a Decoder
S(X,Y,Z) = Σm(1,2,4,7)
C(X,Y,Z) = Σm(3,5,6,7)
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Decoder Expansions
Larger decoders can be constructed using
a number of smaller ones.
-> HIERARCHICAL design!
Example:
A 6-to-64 decoder can be designed using
four 4-to-16 and one 2-to-4 decoders.
How? (Hint: Use the 2-to-4 decoder to
generate the enable signals to the four 4to-16 decoders).
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3-to-8 decoder using two 2-to-4 decoders
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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4-input tree decoder
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Encoders
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An encoder is a digital circuit that
performs the inverse operation of a
decoder. An encoder has 2n input lines
and n output lines.
The output lines generate the binary
equivalent of the input line whose value
is 1.
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Encoders (cont.)
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Encoder Example
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Example: 8-to-3 binary encoder (octal-to-binary)
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
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Encoder Example (cont.)
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Simple Encoder Design Issues
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There are two ambiguities associated with
the design of a simple encoder:
1.
2.
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Only one input can be active at any given time. If
two inputs are active simultaneously, the output
produces an undefined combination (for example,
if D3 and D6 are 1 simultaneously, the output of
the encoder will be 111.
An output with all 0's can be generated when all
the inputs are 0's,or when D0 is equal to 1.
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Priority Encoders
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Solves the ambiguities mentioned above.
Multiple asserted inputs are allowed;
one has priority over all others.
Separate indication of no asserted
inputs.
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Example: 4-to-2 Priority Encoder
Truth Table
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4-to-2 Priority Encoder (cont.)
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The operation of the priority encoder is
such that:
If two or more inputs are equal to 1 at
the same time, the input in the highestnumbered position will take precedence.
A valid output indicator, designated by
V, is set to 1 only when one or more
inputs are equal to 1. V = D3 + D2 + D1 +
D0 by inspection.
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Example: 4-to-2 Priority Encoder
K-Maps
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Example: 4-to-2 Priority Encoder
Logic Diagram
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8-to-3 Priority Encoder
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A Matrix of switches = Keypad
C0
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C1
C2
C3
1
2
3
F
R0
4
5
6
E
R1
7
8
9
D
R2
0
A
B
C
R3
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Keypad Decoder IC - Encoder
COL.
4-bit
1
2
3
F
4
5
6
E
7
8
9
D
0
A
B
C
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4-bit
Binary
(encoded)
ROW
4-bit
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Priority Interrupt Encoder
Schematic
Interrupting
Devices
Interrupt
Encoder
Microprocessor
Device A
Device B
Req(1:0)
Device C
Device D
IntRq
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Priority Encoding - Interrupt
Requests
Interrupting Device
A
B
C
D
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
Req (1:0) IntRq
00
0
00
1
01
1
01
1
10
1
Exercise: Complete this table?
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