CSE477 VLSI Digital Circuits Fall 2002 Lecture 24: RAM Cores

Mary Jane Irwin ( www.cse.psu.edu/~mji www.cse.psu.edu/~cg477 ) [Adapted from Rabaey’s

Digital Integrated Circuits

, ©2002, J. Rabaey et al.]

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Review: Basic Building Blocks

 Datapath  Execution units Adder, multiplier, divider, shifter, etc.

 Register file and pipeline registers  Multiplexers, decoders  Control  Finite state machines (PLA, ROM, random logic)  Interconnect  Switches, arbiters, buses  Memory  Caches (SRAMs), TLBs, DRAMs , buffers

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Review: Read-Write Memories (RAMs)

 Static – SRAM    data is stored as long as supply is applied large cells (6 fets/cell) – so fewer bits/chip fast – so used where speed is important (e.g., caches)  differential outputs (output BL and !BL)  use sense amps for performance  compatible with CMOS technology  Dynamic – DRAM    periodic refresh required small cells (1 to 3 fets/cell) – so more bits/chip slower – so used for main memories  single ended output (output BL only)  need sense amps for correct operation  not typically compatible with CMOS technology

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Review: 4x4 SRAM Memory

2 bit words read precharge enable A 1 A 2 clocking and control A 0

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!BL

BL bit line precharge WL[0] WL[1] WL[2] WL[3] Column Decoder BL[i] BL[I+1] sense amplifiers write circuitry

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6-transistor SRAM Cell

WL M5 M2

!Q

M1 M4

Q

M3 M6 !BL

BL

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SRAM Cell Analysis (Read)

WL=1 M5

!Q=0

M1 M4

Q=1

M6 C bit !BL=1 BL=1 C bit Read-disturb (read-upset) : must carefully limit the allowed voltage rise on !Q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints

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SRAM Cell Analysis (Read)

WL=1 M5

!Q=0

M1 M4

Q=1

M6 C bit !BL=1 BL=1 C bit Cell Ratio (CR) = (W M1 /L M1 )/(W M5 /L M5 ) V !Q

= [(V dd - V Tn )(1 + CR  (CR(1 + CR))]/(1 + CR)

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Read Voltages Ratios

1.2

1 0.8

0.6

0.4

0.2

0 0.3

0.6

0.9

1.2

1.5

Cell Ratio (CR) 1.8

2.1

2.4

V dd V Tn = 2.5V

= 0.5V

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SRAM Cell Analysis (Write)

WL=1 M5

!Q=0

M1 M4

Q=1

M6 !BL=1 BL=0 Pullup Ratio (PR) = (W M4 /L M4 )/(W M6 /L M6 ) V Q = (V dd - V Tn )  ((V dd – V Tn ) 2 – (  p /  n )(PR)((V dd – V Tn - V Tp ) 2 )

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Write Voltages Ratios

1 0.8

0.6

0.4

0.2

0 0.3

0.6

0.9

1.2

1.5

Pullup Ratio (PR) 1.8

2.1

2.4

V dd = 2.5V

|V Tp | = 0.5V

 p /  n = 0.5

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Cell Sizing

 Keeping cell size minimized is critical for large caches  Minimum sized pull down fets (M1 and M3)  Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR  But sizing of the pass transistors increases capacitive load on the word lines a

nd

limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle  Minimum width and length pass transistors  Boost the width of the pull downs (M1 and M3)  Reduces the loading on the word lines and increases the storage capacitance in the cell – both are good! – but cell size may be slightly larger

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6T-SRAM Layout

M2 M4 V DD Q M5 BL M1 Q M3 M6 GND WL BL

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Multiple Read/Write Port Cell

WL1 WL2 M7 M5

!Q

M2 M1 M4

Q

M6 M3 M8 !BL2

!BL1

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BL1 BL2

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4x4 DRAM Memory

2 bit words read precharge enable A 1 A 2 BL clocking, control, and refresh A 0 bit line precharge WL[0] WL[1] WL[2] WL[3] BL[0] BL[1] BL[2] BL[3] sense amplifiers write circuitry Column Decoder

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3-Transistor DRAM Cell

WWL RWL WWL write V dd M3 BL1 M1 C s

X

M2

X

RWL V dd -V t read BL2 V dd -V t BL1 BL2 No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a “1” is V WWL - V tn

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 V

3T-DRAM Layout

BL2 BL1 GND RWL M3 M2 WWL M1

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1-Transistor DRAM Cell

WL C BL M1 C s

X

BL WL write “1”

X

V dd -V t BL V dd /2 V dd read “1” sensing Write: C s is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between C BL and C s Read is destructive, so must refresh after read

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1-T DRAM Cell

Capacitor Metal word line poly

n

+ poly

n

+ Inversion layer induced by plate bias (a) Cross-section SiO 2 Field Oxide M1 word line Diffused bit line Polysilicon Polysilicon plate gate (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area CSE477 L24 RAM Cores.18

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DRAM Cell Observations

 DRAM memory cells are single ended (complicates the design of the sense amp)  1T cell requires a sense amp for each bit line due to charge redistribution read  1T cell read is destructive; refresh must follow to restore data  1T cell requires an extra capacitor that must be explicitly included in the design  A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than V dd )

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Next Lecture and Reminders

 Next lecture  Peripheral memory circuits Reading assignment – Rabaey, et al, 12.3

 Reminders  Project final reports due December 5 th  Final grading negotiations/correction (except for the final exam) must be concluded by December 10 th  Final exam scheduled Monday, December 16 th Thomas from 10:10 to noon in 118 and 121

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