Transcript Slide 1

Add actel spec for HCLK
Can HCLK be tied to power internal to
the Actel FPGA?
Dennis Albaijes
NASA/GSFC
[email protected]
Process
• Write VHDL test code that instantiates the
HCLK buffer and ties its input to power.
• Compile the VDHL Code with ModelSim.
• Synthesize the design with Synplicity.
• Import synthesis netlist to Actel Design tool.
• Compile the netlist with the Actel Design tool.
• IF the netlist complies, place and route the
design and verify the implementation within
the FPGA.
VHDL Code
library ieee;
use ieee.std_logic_1164.all;
library A54SXA;
use A54SXA.components.all;
entity chip is
port (
SIGA
SIGB
: in std_logic; -- input
: in std_logic; -- input
test_out : out std_logic; -- output
SIGC : out std_logic -- output
VHDL code
written to implement
a test design in which
the HCLK input pin
is grounded internally.
);
end entity chip;
architecture behavioral of chip is
component HCLKBUF
port (
PAD
: in std_logic;
Y
: out std_logic
);
end component;
begin
--
Instantiating the Actel global clock buffer
mainclk : HCLKBUF
port map (
PAD
=> '0',
Y
=> test_out
);
SIGC <= SIGA or SIGB; -- create a combinatorial output
end behavioral;
Synthesis Results
0
HCLKBUF
PAD
Y
test_out
mainclk
SIGA
SIGB
SIGC
SIGC
• RTL view of the synthesis shows that the
input of the HCLKBUF is grounded by the
synthesis tool.
• Next, read the netlist into the Actel Design
tool.
Compile Results from Actel Tool
• The Import command succeeded (
00:00:00 )
• ERROR: CMP073: Found Power on
external net: GND...Net: GNDZ0
• There were 1 error(s) and 0 warning(s)
in this design.
• The Compile command failed ( 00:00:01 )
Initial Comments
• Actel tool will not allow an input pin to be tied to
power internal to the chip.
• Previous experience however, has shown that logic
which ultimately goes unused within an FPGA (i.e. it’s
output drives no logic) can be stripped out of design
by the design tool.
• Designer can parse through log files to determine
what, if any, logic has been removed.
• Will modify original code to see if the synthesis tool
will remove an HCLK marco from a design that
connects its input to power yet it’s output drives no
internal logic.
Modified VHDL
library ieee;
use ieee.std_logic_1164.all;
library A54SXA;
use A54SXA.components.all;
entity chip is
port (
SIGA
SIGB
--
Original code
modified such that
the HCLK input pin
is still grounded internally,
but the output of the clock
driver is not connected to
any internal design nets.
: in std_logic; -- input
: in std_logic; -- input
test_out : out std_logic; -- output
SIGC : out std_logic -- output
);
end entity chip;
architecture behavioral of chip is
component HCLKBUF
port (
PAD
: in std_logic;
Y
: out std_logic
);
end component;
signal test
: std_logic;
begin
--
Instantiating the Actel global clock buffer
mainclk : HCLKBUF
port map (
PAD
=> '0',
Y
=> test -- output of HCLK is not tied to internal logic
);
SIGC <= SIGA or SIGB; -- create a combinatorial output
end behavioral;
Synthesis results
SIGA
SIGB
SIGC
SIGC
• Synplicity detects that the HCLK does not
drive any internal logic so it is removed
from the design.
• Synplicity reports the following :
@W: CL168
:"C:\Projects\Design_Methodology\VHDL\
HCLK_TEST2.vhd":107:6:107:12 |Pruning
instance mainclk - not in use ...
Compile Results with revised code
•
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Created a new design.
The Import command succeeded ( 00:00:00 )
Post-Combiner device utilization:
SEQUENTIAL
Used: 0 Total: 1080 (0.00%)
COMB
Used: 1 Total: 1800 (0.06%)
LOGIC
Used: 1 Total: 2880 (0.03%) (seq+comb)
IO w/ Clocks Used: 3 Total: 170
CLOCK
Used: 0 Total: 2
HCLOCK
Used: 0 Total: 1
There were 0 error(s) and 0 warning(s) in this design.
• The Compile command succeeded ( 00:00:02 )
Conclutions
• Exercise shows that it is not possible to internally connect
power to the HCLK buffer.
• Errors will be generated by the Actel Design tool and the design
will not compile.
• Actel data sheet states that “If not used, the pin must be set
LOW or HIGH on the board.”
• Exercise also shows that a designer can code a design which
connects the HCLK input to power. However, if the output of the
driver is not connected to internal logic it will be removed during
synthesis. This will result in a design in which the HCLK pin is
left floating.
• Fibertek has either discovered a work around or is not aware
that the HCLK marco was removed by the design tools.
• Design files are necessary to determine what is actually being
implemented.