Transcript A System‐Level Stochastic Benchmark Circuit Generator for
A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research
Cindy Mark Prof. Steve Wilton
University of British Columbia Supported by Altera and NSERC
Introduction: Overview FPGA architecture studies require benchmark circuits Realistic, big, and varied Current circuits are small MCNC: 24 LE to 7694 LE Stratix III: 19,000 LE to 135,200 LE Alternatives ASIC: requires conversion Synthetic: designed for sizes similar to MCNC circuits
Contribution
: SOC synthetic circuit generator Glues modules into realistic, big netlists Allows customization of the circuit content
Research Approach
Survey of Circuit Designs Generator Development
Circuit Characterization: Survey 66 Block Diagrams 24 industrial 42 academic Applications: Communication Multimedia Processor
Circuit Model
Leaf Modules Processor Interface Controller Cores Networks Bus Dataflow Star Leaf modules connected by networks Networks are hierarchical, and arranged in a tree
Circuit Model: Example BUS BUS CPU CORE CORE CORE CORE
Circuit Characterization: Trends 50 40 30 20 10 0 Hierarchy Depth Distribution 1 2 Hierarchy Depth 3
Circuit Characterization: Trends Max Hier. Depth 1 2 3 4 Average # Networks 1 1.81
1.75
2.16
20 Network # Distribution on Level 2 16 12 8 4 0 1 2 3 4 Number of Networks 5 6
Circuit Characterization: Trends 12
Number of Modules per Bus
9 6 3 0 0 5 10 Number of Blocks 15
Number of Modules per Dataflow
20 15 10 5 4 3 2 0 0 1 2 3 4 5 6 7 9 101112 Number of Blocks 17
Number of Modules per Star
5 1 0 2 3 4 5 7 Number of Blocks 13
Generation
Circuit Generator: Overview Interface Generator Constraints Complete Circuit Definition Generator BLIF libraries Constraints file: # hierarchy levels, # blocks, # networks, bus width Can specify any combination One BLIF library directory per module type BLIF Circuit
Circuit Generation: Example 50 40 30 20 10 0 1 2 Hierarchy Depth 1 0.8
0.6
0.4
0.2
3 0
Circuit Generator: Implementation Modules MCNC OpenCores Synthetic Networks Bus: AMBA single master Dataflow: with feedback Star: no feedback
Circuit Generator: Implementation Where are the fine grained connections?
Some generated through the network process Reset Interrupt
Comparison: Overview Evaluation of SOC circuits as they scale Comparison to other synthetic generators
GEN
: purely combinational
GNL
: FFs and IOs Characteristics Post-Routing: channel width, wirelength, crit. path
Results: Locality New GNL
Results: Average Wirelength 60.00
50.00
40.00
30.00
20.00
10.00
0.00
0 10000 20000 30000
Size of Circuit
40000 NEW GEN GNL 50000 60000
Results: Channel Width 140 120 100 80 60 40 20 0 0 10000 20000 30000
Size of Circuit
40000 NEW GEN GNL 50000 60000
Results: Critical Path Delay 120.00
100.00
80.00
60.00
40.00
20.00
0.00
0 10000 20000 30000
Size of Circuit
40000 NEW GEN GNL 50000 60000
Conclusion: Limitations High number of IO pins Caused by star networks Mismatch between bus width and module IO pins Head and tail of dataflow networks
Conclusion: Ongoing work Add different block types (memory) Add different network types Improve the modeling of reset, interrupt Improve the modeling of blocks
Conclusion: Status Can generate circuits 150k LE and up Works on Linux / Windows Works better on Linux Manual Available for download: www.ece.ubc.ca/~cindym/
Conclusion: Summary We have developed a synthetic SOC circuit generator suitable for architectural research Based on an analysis of published block diagrams Assumes a tree-like network hierarchy that connects existing BLIF blocks Resulting circuits, in general, display slower growth in complexity and post-routing characteristics relative to GEN and GNL.
Thank You!
Results: Rent Parameter 0.90
0.85
0.80
0.75
0.70
0.65
0.60
0 10000 20000 30000
Size of Circuit
NEW GEN 40000 GNL 50000 60000
Results: Nets (post-clustering) 70000 60000 50000 40000 30000 20000 10000 0 0 10000 20000 30000
Size of Circuit
40000 NEW GEN GNL 50000 60000