Transcript 7-6 Microoperations on a single register

7-7 Register-Cell Design
A single-bit cell of an iterative combinational circuit
connected to a flip-flop that provides the output
forms a two-state sequential circuit called a register
cell.
Example 7-1 Register-cell design
A register A and is to implement the following
register transfers with an input B :
AND : A  A  B
EXOR: A  A  B
OR : A  A  B
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Example 7-1
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Assumption
 Only one of AND, EXOR, and OR is equal to 1
 For all AND, EXOR, and OR equal to 0, the content
of A remains unchanged
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Example 7-1
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One solution
 LOAD=AND+EXOR+OR
 Di  A(t  1)i  AND Ai Bi  EXOR ( Ai Bi  Ai Bi )  OR  ( Ai  Bi )
From Table 7-11, we can rewrite the solution as
Di  A(t  1) i  AND  Ai Bi  EXOR ( Ai Bi  Ai Bi )  OR  ( Ai  Bi )
 AND  EXOR OR  Ai
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Example 7-1
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Simplify the equation
 Share
the control variables to all register cells
since they are the same for each cell
 Simplification from 2nd solution in the previous
slide
Di  C1 Ai Bi  C3 Ai Bi  C 2 Ai Bi
C1  OR  AND  EXOR
C 2  OR  EXOR
C3  C 2  AND
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Example 7-1
 Simplification
from the 1st solution in slide
page 3
Di  C1 Ai Bi  C 2 Ai Bi  C 2 Ai Bi
C1  OR  AND
C 2  OR  EXOR
LOAD  C1  C 2
Di , FF  LOAD Di  LOAD Ai
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Example 7-1
Use the simplification in slide page 4 can
save about 40% (for 16 cells) gate cost
and hence time delay compared to those
by using the simplification in slide page 5.
 Why?
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Example 7-2
A register A is to implement the following
register transfers with an input B :
SHL : A  sl A
EXOR : A  A  B
ADD: A  A  B
Assumption:
•Only one of SHL, EXOR, and ADD is equal to 1
•For all SHL, EXOR, and ADD equal to 0, the content of
A remains unchanged
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Example 7-2
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Solution
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LOAD=AND+EXOR+OR
Di  A(t  1) i  SHL Ai 1  EXOR ( Ai  Bi )  ADD (( Ai  Bi )  Ci )
Ci 1  ( Ai  Bi )Ci  Ai Bi
Another solution (combine ADD and SHL (share Ci))

Di  A(t  1) i  SHL EXOR ADD Ai  SHL Ci  EXOR ( Ai  Bi )
 ADD (( Ai  Bi )  Ci )

Ci 1  SHL Ai  ADD(( Ai  Bi )Ci  Ai Bi )
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Example 7-2

Simplification (from 2nd solution in previous
slide) (Ci=0 for EXOR)
Di  E 2  Ai  SHL Ci  E1  (( Ai  Bi )  Ci )
E1  EXOR ADD
E 2  E1  SHL
Ci 1  SHL Ai  ADD(( Ai  Bi )Ci  Ai Bi )
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7-8 Multiplexer and
bus-based transfers
for multiple register
Dedicated multiplexer
 2n AND gate cost and
n OR gate cost per
multiplexer
 Total of 9n gate cost
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Single bus
3n AND gate cost
and n OR gate
cost
 Total of 4n gate
cost
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Single bus
Note: The 3rd case in the table is possible for dedicated
multiplexer architecture
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Three-state bus
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7-9 Serial transfer and
Microoperations
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Information in a system is transferred or
manipulated one bit at a time
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Serial transfer
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Serial Addition
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We are now neglecting the following
two sections
7-10 Two design examples
7-11 HDL
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7-13 Microprogrammed Control
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A control unit with its binary control values stored
as words in memory
Each word in the control memory contains a
microinstruction
A microinstruction specifies one or more
microoperations for a system
A sequence of microinstructions constitutes a
microprogram
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Two registers
Control address register (CAR): a register
specifies the address of the
microinstruction
 Control data register (CDR): a register
holds the microinstruction currently being
executed by the datapath and the control
unit
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Next-address generator
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When a microinstruction is executed, the nextaddress generator produces the next address
The address of next instruction to be executed
may be next one or located somewhere else in
the control memory
A function of control word is to determine the
address of the next microinstruction to be
executed
Sometimes it is called sequencer
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Microprogrammed control unit
organization
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CISC
A simple instruction set computer (SISC)
as introduced above can’t fit the complex
applications for today’s computer.
 A complex instruction set computer (CISC)
has emerged (Chap. 11)
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