Transcript Slide 1

CS 105
DIGITAL LOGIC
DESIGN
Chapter 4
Combinational Logic
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Outline
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4.1 Introduction.
4.2 Combinational Circuits.
4.3 Analysis Procedure.
4.4 Design Procedure.
4.5 Binary Adder-Subtractor.
4.6 Decimal Adder.
4.7 Binary Multiplier.
4.9 Decoders.
4.10 Encoders.
4.11 Multiplexers.
4.1 Introduction (1-2)
 Logic
circuits for digital systems may be combinational or
sequential.
Combinational Circuit
 Consists of logic gates whose outputs at any time are
determined from only the present combination of inputs.
 Performs an operation that can be specified logically by a
set of Boolean functions.
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4.1 Introduction (2-2)
Sequential Circuit
 Employs storage elements in addition to logic gates.
 Their outputs are a function of the inputs and the state of
the storage elements.
 Because the state of the storage elements is a function of
previous inputs, the outputs of a sequential circuit depend
not only on present value of inputs, but also on past inputs.
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4.2 Combinational Circuit (1-2)
Input Variables
Consists of:
Logic Gates
Output Variables
Transforms input data into required output data.
n inputs
.
.
Combinational
circuits
Block diagram
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.
.
m outputs
4.2 Combinational Circuit (2-2)
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n input variables  2n binary input combinations.
Each possible combination  one possible combination output.
Combinational circuit can be specified with truth table.
Combinational circuit can be described by m Boolean functions.
Each output function is expressed in terms of the n input
variables.
Standard Combination Circuits
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Adders, subtractors, comparators, decoders, encoders and
multiplexers
4.3 Analysis Procedure (1-4)
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Determine the function that the circuit implements from a logic diagram.
Circuit’s function can be determined by either Boolean function or truth
table.
Steps
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Make sure that it is combinational not sequential.
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No memory elements.
No feedback path (feedback path: a connection from the output of one gate
to the input of a second gate that forms part of the input to the first gate).
Obtain Boolean function or the truth table.
4.3 Analysis Procedure (2-4)
Boolean function
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4.3 Analysis Procedure (4-4)
Truth Table
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4.4 Design Procedure (1-7)
Steps
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State the problem.
From the specifications of the circuit, determine the required number of
inputs and outputs and assign a symbol to each.
Derive the truth table that defines the required relationship between
inputs and outputs.
Obtain the simplified Boolean functions for each output as a function
of the input variables.
Draw the logic diagram and verify the correctness of the design
4.4 Design Procedure (2-7)
Example
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Design a circuit that converts binary coded decimal (BCD) to the
excess-3 code for the decimal digits.
Inputs
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BCD (4 bits).
4 inputs.
Symbols: A, B, C, D.
Outputs
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Ex-3 (4 bits).
4 outputs.
Symbols: w, x, y, z.
4.4 Design Procedure (7-7)
Logic Diagram
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4-5 Binary Adder-Subtractor (1-20)
Binary Adder-Subtractor
 Is
a combinational circuit that performs the arithmetic
operations of addition and subtraction with binary
numbers.
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4-5 Binary Adder-Subtractor (2-20)
Half adder
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Is a combinational circuit that performs the addition of two bits.
Elementary Operations
0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1+ 1 = 10
Truth Table
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two input variables
 x, y.
two output variables.
 C (output carry), S (least
significant bit of the sum).
4-5 Binary Adder-Subtractor (3-20)
Half adder
Simplified Boolean Function
(Sum of Products)
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S = x'y+xy'
C = xy
Logic Diagram (Sum
of Products)
4-5 Binary Adder-Subtractor (4-20)
Half adder
Simplified Boolean Function (XOR
and AND gates)
S=xy
C = xy
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Logic Diagram
(XOR and AND gates)
4-5 Binary Adder-Subtractor (5-20)
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Functional Block: Full-Adder
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It is a combinational circuit that performs the arithmetic sum of three bits
(two significant bits and previous carry).
It is similar to a half adder, but includes a carry-in bit from lower
stages.
Two half adders can be employed to implement a full adder.
Inputs & Outputs
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Three input bits:
 x, y : two significant bits
 Z : the carry bit from the previous lower significant bit.
Two output variables:
 C (output carry), S (least significant bit in sum).
4-5 Binary Adder-Subtractor (6-20)
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Functional Block: Full-Adder
Operations
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For a carry-in (Z) of
0, it is the same as
the half-adder:
For a carry- in
(Z) of 1:
Z
X
+Y
0
0
+0
0
0
+1
0
1
+0
0
1
+1
CS
00
01
01
10
Z
X
+Y
1
0
+0
1
0
+1
1
1
+0
1
1
+1
CS
01
10
10
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4-6 Decimal Adder (1-4)
BCD Adder
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Add two BCD‘s:
 9 inputs: two BCD's and one carry-in.
 5 outputs: one BCD and one carry-out.
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Design approaches
 Use unary full Adders.
 A truth table with 29 entries
 Each input digit does not exceed 9.
 The output sum connot be greater than 9.
 e.g. 9 + 9 + 1 =19 , the 1 in sum being an input carry.
 The output of the binay sum must be represented in BCD.
4-6 Decimal Adder (2-4)
BCD Adder
Truth Table
4-6 Decimal Adder (4-4)
BCD Adder
Logic Diagram
4-7 Binary Multiplier (1-4)
Multiplication of binary numbers is performed in the same
way of decimal numbers.
Example
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Consider the multiplication of two 2-bit numbers.
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Multiplicand bits are B0 and B1.
Multiplier bits are A0 and A1.
The product is C3C2C1C0.
4-7 Binary Multiplier (2-4)
Logic Diagram
 The
partial product
can be implemented
with AND gates.
 The two partial
products are added
with two half-adder
(HA) circuits.
4-7 Binary Multiplier (3-4)
J-Bit by K-Bit Binary Multiplier
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For J multiplier bits and K multiplicand bits to produce J +
K bits , we need :
 J x K AND gates.
 (J-1) K-bit adders.
Example (4-Bit by 3-Bit Multiplier)
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Multiplicand : B3B2B1B0
Multiplier: A2A1A0
12 AND gates
2 four-bit adders.
Produces product of 7 bits
4-7 Binary Multiplier (4-4)
Example (4-Bit by 3-Bit Multiplier)
4-9 Decoder (1-16)
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Discrete quantities of information are represented in digital
systems by binary codes.
A binary code of n bits is capable of representing up to 2n distinct
elements of coded information.
Decoder
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Is a combinational circuit that converts the binary information from
n input lines to a maximum of 2n unique output lines.
If the n-bit coded information has unused combinations, the
decoder may have fewer than 2n outputs.
Called n-to-m-line decode, where m <= 2n minterms of n input
variables.
4-9 Decoder (2-16)
Example
Consider three-to-eight-line decoder circuit
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Inputs = 3.
Outputs = 8 (minterms)
Truth Table
ONLY one output can be
active at any time
Example:
Binary – to –octal
decoder
4-9 Decoder (3-16)
Logic Diagram
4-9 Decoder (4-16)
NAND gates
Generates decoder minterms in their complemented form
4-9 Decoder (5-16)
Demultiplixers
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A decoder with one or more enable (E) inputs.
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Control the circuit operation.
E =0, Decoder is disabled.
E =1, Decoder is enabled.
A circuit that receives information from a single Line and directs it
to one of 2n possible output lines.
4-9 Decoder (6-16)
Demultiplixers
Design a two-to-four-line decoder with an enable input.
Truth table
Uncomplemented
output
E
A
B
D0
D1
D2
D3
0
X
X
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
4-9 Decoder (7-16)
Demultiplixers
Design a two-to-four-line decoder with an enable input.
Logic Diagram
4-9 Decoder (8-16)
Demultiplixers
Design a two-to-four-line decoder with an enable input constructed
with NAND gates.
Truth table
Complemented
output
E
A
B
D0
D1
D2
D3
1
X
X
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
1
0
4-9 Decoder (9-16)
Demultiplixers
Design a two-to-four-line decoder with an enable input constructed
with NAND gates.
Logic Diagram
4-9 Decoder (10-16)
Demultiplixers
Design a 4-to-16 decoder.
Design a 4-to-16 decoder using two 3-to-8 decoders.
4-9 Decoder (12-16)
Demultiplixers
Design a 5-to-32 line decoder using four 3-to-8 line decoders with
enable inputs and a 2-to-4 line decoder.
A0
3-8-line
Decoder
E
A1
A2
A3
A4
D0 – D7
3-8-line
Decoder
E
D8 – D15
3-8-line
Decoder
E
D16 – D23
3-8-line
Decoder
E
D24 – D31
2-4-line
Decoder
4-9 Decoder (13-16)
Combinational Logic Implementation
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Each output = minterm.
Implementing Boolean function (expressed in sum of minterms) by
using:
 A decoder .
 An external OR gate.
Any combinational circuit with n inputs and m outputs can be
implemented with an n-to-2n-line decoder and m OR gates.
4-9 Decoder (14-16)
Combinational Logic Implementation
Design a full adder using a decoder.
4-10 Encoder (1-7)
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Is a digital circuit that performs the inverse operation of a
decoder.
An encoder has 2n (or fewer) input lines and n output lines.
Example
Design an octal-binary encoder
4-10 Encoder (2-7)
Example
Design an octal-binary encoder
4-10 Encoder (3-7)
Limitations on previous example
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If two inputs are active simultaneously, the output produces an
undefined combination.
• E.g. if D3 and D6 are 1 simultaneously, the output of the encoder
will be 111.
• Resolve this ambiguity, establish an input priority to ensure. D6
will be the higher priority.
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Output with all 0's is generated when:
• All the inputs are 0
• D0 is equal to 1.
• Resolve by providing one more output to indicate whether at least
one input is equal to 1.
4-10 Encoder (4-7)
Priority Encoder
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Is an encoder circuit that includes the priority function.
Resolve the ambiguity of illegal inputs.
if two or more inputs are equal o 1 at the same time. the input
having the highest priority will take precedence.
4-10 Encoder (5-7)
Priority Encoder
Design an four –to - two priority encoder
4-11 Multiplexer (1-15)
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is a combinational circuit that selects a binary information from one of
many input lines and directs it to a single output line.
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The selection of a particular input line is contro1led by a set of
selection lines.
•
2n input lines and n selection lines whose bit combinations determine
which input is selected.
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Also called a data selector, since it selects one of many inputs and
steers the binary information to the output line.
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The size of a multiplexer is specified by the number 2n of its
data input lines and the single output line.
4-11 Multiplexer (2-15)
Example
Design a 2 –to-1 line MUX
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Data Inputs = 21=1
Selection Input= 1
Output = 1
Function Table
S0
Y
0
I0
1
I1
4-11 Multiplexer (3-15)
Example
Design a 4 –to-1 line MUX
Function Table
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Data Inputs = 22 =4
Selection Input= 2
Output = 1
4-11 Multiplexer (4-15)
Example
Design a 4 –to-1 line MUX
4-11 Multiplexer (5-15)
Notes
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2n – to – 1 MUX can be implemented using decoder:
•
•
•
•
•
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Decode selection input lines.
n (selection input lines) – to - 2n decoder.
Adding the 2n input lines to each AND gate.
OR all AND gates.
An enable input (an option).
Multiplexers may have an enable input to control the operation
of the unit
• When the enable input is in the inactive state, the outputs are
disabled.
• When it is in the active state, the circuit functions as a normal
multiplexer.
4-11 Multiplexer (6-15)
Example
Design an 8–to-1 line MUX using a 3-to-8 line decoder.
4-11 Multiplexer (7-15)
Multiple bit Selection
 Multiplexer
circuits can be combined with common selection
inputs to provide multiple-bit selection logic.
 E.g. quadruple 2-to-1 line MUX.
4-11 Multiplexer (8-15)
Quadruple
2-to- 1 -line
multiplexer.
4-11 Multiplexer (9-15)
Boolean Function Implementation
 Boolean
function with n variables can be implemented with
a multiplexer that has:
• n-1 selection inputs.
• 2n-1 data inputs.
 The
first n-1 variables connected to the selection inputs of
the MUX.
 The remaining single variable of the function is used for the
data inputs.
• If the single variable is denoted by z , each data
input of the MUX will be z,z’,1 or 0.
4-11 Multiplexer (10-15)
Example
Implment the following function using a MUX
F(A,B,C) =S(1,2,6,7)
Implment the following function using a MUX
F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15)
Fig. 4.27
4-11 Multiplexer (12-15)
Three-State Gates
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A multiplexer can be constructed with three-state gates.
Output state: 0, 1, and high-impedance (open circuit)
When the control input =1 :
• The output is enabled.
• The gate behave like a conventional buffer, with the output is equal to
normal input.

When the control input=0 :
• The output is disabled
• The gate goes to a high-impedance state , regardless the value of the
normal input.
4-11 Multiplexer (13-15)
Example
Two -to-one-line multiplexer with three state gates
4-11 Multiplexer (14-15)
Example
Four-to-one-line multiplexer using decoder with three state gates
4-11 Multiplexer (15-15)
Example
Four-to-one-line multiplexer with three state gates
 The control inputs to the buffers determine which one of the four
normal inputs I0 to I3 will be connected to output line.
 No more than one buffer may be in the active state at any given time.
 The connected buffers must be controlled so that only 1 thee-state
buffer has access to the output while all other buffers are maintained
in a high-impedance state.
 One way to ensure that no more than one control input is active at any
given time is to use a decoder .
 When E=0  high impedance state (all buffers are disable)
 When E=1 one of the three buffers will be active.