Transcript The Design of Survivable Networks

ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
Lecture 7
Dr. Shi
Dept. of Electrical and Computer Engineering
BINARY ADDERS
Overview

Addition of binary data is fundamental
 Need

to determine hardware implementation
Represent inputs and outputs
 Inputs:
single bit values, carry in
 Outputs: Sum, Carry

Hardware features
 Create

a single-bit adder and chain together
Dealing with overflow
 What
happens if numbers are too big?
4-Bit Adder
Think top-down: How to break a problem into pieces?
Multiple-bit Addition
Consider single-bit adder for each bit position.
A3 A2 A1 A0
B3 B2 B1 B0
A 0 1 0 1
A
B
1
0
0
1
1
1
1
1
1
0 1
1 1
0 0
B 0 1 1 1
Ci+1
Ci
Ai
+Bi
Si
Each bit position creates a sum and carry
Full Adder
Single-bit full adder, building block of large adders
Common piece of computer hardware
Block Diagram
Full Adder
Full adder includes carry in Ci
Notice interesting pattern in Karnaugh map.
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
AiBi
00
Ci
11
1
0
1
01
10
1
1
1
Si
Full Adder
Now consider implementation of carry out
Two outputs per full adder bit (Ci+1, Si)
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
AiBi
00
Ci
01
1
1
Ci+1
Note: 3 inputs
10
1
0
1
11
1
Full Adder Implementation
Si = Ci (Ai  Bi)
Ci+1 = Ai · Bi + Ci · (Ai  Bi)
Full Adder
Hardware repetition simplifies hardware design
A full adder can be made from
two half adders (plus an OR gate).
4-Bit Adder
Chain single-bit adders together.
What does this do to delay?
C
A
B
S
1
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
Half Adder (not very useful)
Add two binary numbers
• A0 , B0 -> single bit inputs
• S0 -> single bit sum
• C1 -> carry out
A0
B0
A0 B0 S0 C 1
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
S0
C1
Dec Binary
1
+1
2
1
+1
10
Multiplexers
Multiplexers




Select an input value with one or more select bits
Use for transmitting data
Allows for conditional transfer of data
Sometimes called a mux
4– to– 1- Line Multiplexer
Quadruple 2–to–1-Line Multiplexer
Notice enable bit
Notice select bit
4 bit inputs
Multiplexer as combinational modules



Connect input variables to select inputs of multiplexer (n-1
for n variables)
Set data inputs to multiplexer equal to values of function for
corresponding assignment of select variables
Using a variable at data inputs reduces the size of the
multiplexer
Implementing a Four- Input Function with a Multiplexer
Multiplexers & Shannon Expansion
Shannon Expansion Theorem


The Shannon expansion develops the idea that Boolean functions can be
reduced by means of the identity:
where F is any function and Fx and Fx' are Shannon cofactors of F.
Example
f = yz + xyz' + x'y'z
= yz(x' + x) + xyz' + x'y'z
= x'yz + xyz + xyz' + x'y'z
= x'(yz + y'z) + x(yz + yz')
= x'gx' + xgx
Expand about 2 variables
Multiplexer Implementation
DECODERS
Overview

Binary decoders
 Converts
an n-bit code to a single active output
 Can be developed using AND/OR gates
 Can be used to implement logic circuits.

Binary encoders
one of 2n inputs to an n-bit output
 Useful for compressing data
 Can be developed using AND/OR gates
 Converts

Both encoders and decoders are extensively used in
digital systems
Binary Decoder


Black box with n input lines and 2n output lines
Only one output is a 1 for any given input
n
inputs
Enable
Binary
Decoder
2n outputs
2-to-4 Binary Decoder
Truth Table:
F0 = X'Y'E
Enable = 1
F1 = X'YE


From truth table, circuit for 2x4
decoder is:
F2 = XY'E
Note: Each output is a 2variable minterm (X'Y', X'Y, XY'
or XY)
F3 = XYE
Enable
F0
X
Y
2-to-4
Decoder
F1
F2
F3
Enable
X
Y
3-to-8 Binary Decoder
Truth Table:
Enable = 1
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
F0 F1 F2 F3 F4 F5 F6 F7
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
F0 = x'y'z’E
F1 = x'y'zE
F2 = x'yz'E
F3 = x'yzE
F4 = xy'z'E
F5 = xy'zE
F0
F1
X
Y
Z
3-to-8
Decoder
F6 = xyz'E
F2
F3
F7 = xyzE
F4
F5
F6
F7
Enable
Enable
x
y
z
Implementing Functions Using Decoders

Any n-variable logic function can be implemented using a single
n-to-2n decoder to generate the minterms
 OR
gate forms the sum.
 The output lines of the decoder corresponding to the
minterms of the function are used as inputs to the or
gate.


Any combinational circuit with n inputs and m outputs can be
implemented with an n-to-2n decoder with m OR gates.
Suitable when a circuit has many outputs, and each output
function is expressed with few minterms.
Implementing Functions Using Decoders

Example: Full adder
S(x, y, z) = S (1,2,4,7)
C(x, y, z) = S (3,5,6,7)
Enable = 1
3-to-8 0
Decoder 1
x
S2
y
S1
z
S0
Enable
2
3
4
5
6
7
x
y
z
C
S
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
S
C
Use two 3 to 8 decoders to make 4
to 16 decoder


In this example, only one decoder can be active
at a time.
x, y, z effectively select output line for w
Encoders
Encoders


If the a decoder's output code has fewer bits than
the input code, the device is usually called an
encoder. e.g. 2n-to-n
The simplest encoder is a 2n-to-n binary encoder


One of 2n inputs = 1
Output is an n-bit binary number
2n
inputs
.
.
.
Binary
encoder
.
.
.
n
outputs
8-to-3 Binary Encoder
Inputs
At any one time, only
one input line has a value of 1.
I0
1
0
0
0
0
0
0
0
I1
0
1
0
0
0
0
0
0
I2
0
0
1
0
0
0
0
0
I3
0
0
0
1
0
0
0
0
I4
0
0
0
0
1
0
0
0
Outputs
I5
0
0
0
0
0
1
0
0
I6
0
0
0
0
0
0
1
0
I0
I1
y 2 = I4 + I 5 + I6 + I7
I2
I3
y 1 = I2 + I 3 + I6 + I7
I4
I5
I6
I7
y 0 = I1 + I 3 + I5 + I7
I7
0
0
0
0
0
0
0
1
y2
0
0
0
0
1
1
1
1
y1
0
0
1
1
0
0
1
1
y0
0
1
0
1
0
1
0
1
8-to-3 Priority Encoder
• What if more than one input line has a value of 1?
• Ignore “lower priority” inputs.
• Idle indicates that no input is a 1.
Inputs
I0
0
1
X
X
X
X
X
X
X
I1
0
0
1
X
X
X
X
X
X
I2
0
0
0
1
X
X
X
X
X
I3
0
0
0
0
1
X
X
X
X
I4
0
0
0
0
0
1
X
X
X
Outputs
I5
0
0
0
0
0
0
1
X
X
I6
0
0
0
0
0
0
0
1
X
I7
0
0
0
0
0
0
0
0
1
y2
x
0
0
0
0
1
1
1
1
y1
x
0
0
1
1
0
0
1
1
y0
x
0
1
0
1
0
1
0
1
Idle
0
1
1
1
1
1
1
1
1
Priority Encoder (8 to 3 encoder)

Priority Encoder :
H7=I7
(Highest Priority)
H6=I6·I7’
H5=I5·I6’ ·I7’
H4=I4·I5’ ·I6’·I7’
H3=I3.I4’·I5’ ·I6’·I7’
H2=I2.I3’·I4’ ·I5’·I6’ ·I7’
H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’
H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’
IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’
Inputs
I0
0
1
X
X
X
X
X
X
X
I1
0
0
1
X
X
X
X
X
X
I2
0
0
0
1
X
X
X
X
X
I3
0
0
0
0
1
X
X
X
X
I4
0
0
0
0
0
1
X
X
X
Outputs
I5
0
0
0
0
0
0
1
X
X
I6
0
0
0
0
0
0
0
1
X
I7
0
0
0
0
0
0
0
0
1
y2 y1 y0
x x x
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Idle
0
1
1
1
1
1
1
1
1
I0
H0
I1
H1
I2
H2
I3
H3
I4
H4
I5
H5
I6
H6
I7
H7
IDLE
Priority Encoder (8 to 3 encoder)




Assign priorities to the inputs
When more than one input are asserted, the output generates the code of the
input with the highest priority
Priority Encoder :
H7=I7
(Highest Priority)
H6=I6·I7’
H5=I5·I6’ ·I7’
H4=I4·I5’ ·I6’·I7’
I0
H3=I3.I4’·I5’ ·I6’·I7’
I1
H2=I2.I3’·I4’ ·I5’·I6’ ·I7’
I2
H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’
I3
H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’
IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’ I4
Encoder
Y0 = I1 + I3 + I5 + I7
Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7
Priority encoder
Priority Circuit
Binary encoder
I0
H0
I0
I1
H1
I1
I2
H2
I2
Y0
Y0
I3
H3
I3
Y1
Y1
I4
H4
I4
Y2
Y2
I5
I5
H5
I5
I6
I6
H6
I6
I7
I7
H7
I7
IDLE
IDLE