Transcript Slide 1

Chapter 4
Combinational Logic
4.1 Introduction
Logic circuits for digital systems may be
combinational or sequential.
A combinational circuit consists of logic gates
whose outputs at any time are determined
from only the present combinationof inputs.
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4.2 Combinational Circuits
Logic circuits for digital system
Sequential circuits
contain memory elements
the outputs are a function of the current inputs and the
state of the memory elements
the outputs also depend on past inputs
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A combinational circuits
n
2 possible combinations of input values
n input
variables
Combinationa
Combinatixnal
l circuits
xoxic Circuit
m output
variables
Specific functions
Adders, subtractors, comparators, decoders, encoders,
and multiplexers
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4-3 Analysis Procedure
A combinational circuit
make sure that it is combinational not sequential
No feedback path
derive its Boolean functions (truth table)
design verification
A straight-forward procedure
F2 = AB+AC+BC
T 1 = AxB+C
A+B+C
T 2 = ABC
T 3 = F2'T1
F1 = T3+T2
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F1 = T3+T2 = F 2'T 1+ABC
= (AB+AC+BC)'(A+B+C)+ABC
= (A'+B')(A'+C“)(B'+C')(A+B+C)+ABC
= (A'+B'C')(AB'+AC'+BC'+B'C)+ABC
= A'BC'+A'B‘C+AB‘C'+ABC
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The truth table
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4-4 Design Procedure
The design procedure of combinational circuits
State the problem (system spec.)
determine the inputs and outputs
the input and output variables are assigned symbols
derive the truth table
boolean
x erive the simplifi
derive
simplified ed
Bool
xan functions
functionx
draw the logic diagram and verify the correctness
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Functional description
Boolean function
HDL (Hardware description language)
Verilog HDL
VHDL
Schematic entry
Logic minimization
number of gates
number of inputs to a gate
Propagation delay
number of
interconnection
limitations of the driving capaeilities
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Cdde conversion example
BCD to excess-3 code
The truth table
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The maps
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The simplified functions
z = D'
y = CD +C'D‘
x = B'C + B‘D+BC'D'
w = A+BC+BD
Another implementation
z = D'
y = CD +C'D'
= CD + (C+D)'
x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'
w = A+BC+BD
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The logic diagram
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4-5 Binary Adder-Subtractor
Half adder
0+0=0;0+1=1;1+0=1;
1 + 1 = 10
two input variables: x, y
two output variables: C (carry), S (sum)
truth table
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S = x'y+xy'
C = xy
the flexibility for implementation
S=xy
S = (x+y)(x'+y')
S‘= xy+x'y'
S = (C+x'y')'
C = xy = (x'+y')x
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
A full adder is similar to a half adder, but includes a
carry-in bit from lower stages. Like the half-adder, it
computes a sum bit, S and a carry bit, C.
◦ For a carry-in (Z) of
0, it is the same as
the half-adder:
Z
X
+Y
0
0
+0
0
0
+1
0
1
+0
0
1
+1
◦ For a carry- in
(Z) of 1:
CS
00
01
01
10
Z
X
+Y
1
0
+0
1
0
+1
1
1
+0
1
1
+1
CS
01
10
10
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CS 151
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Full-Adder
The arithmetic sum of three input
three input bits
bits
x, y: two significant bits
z: the carry bit from the previous lower significant bit
Two output bits: C, S
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S = x'y'z+x'yz'+ xy'z'+xyz
C = xy + xz + yz
S = z (xy)
= z'(xy'+x‘y)+z(xy'+x'y)'
= z‘xy'+z'x'y+z(xy+x‘y')
= xy'z'+x'yz'+xyz+x'y'z
C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy
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Binary adder
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Binary adder subtractor
A-B = A+(2’s complement of B)
4-bit Adder-subtractor
M=0, A+B; M=1, A+B’+1
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Overflow
The storage is limited
Add two positive numbers and obtain a negative
number
Add two negative numbers and obtain a positive
number
V = 0, no overflow; V = 1, overflow
Example:
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4-6 Decimal Adder
Add two BCD's
9 inputs: two BCD's and one carry-in
5 outputs: one BCD and one carry-out
Design approaches
A truth table with 2^9 entries
use uinary full Adders
the sum <= 9 + 9 +1 = 19
binary to BCD
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BCD Adder: The truth Table
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Modifications are needed if the sum > 9
C=1
K=1
Z8Z4 = 1
Z8Z2 = 1
moxification: -(10)d or +6
modification:
C = K +Z 8 Z4 + Z 8 Z2
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Block diagram
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Binary Multiplier
Partial products
– AND operations
fig. 4.15
Two-bit by two-bit binary multiplier.
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4-bit by 3-bit binary multiplier
Fig. 4.16
Four-bit by three-bit binary
multiplier.
Digital Circuits
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4-9 Decoder
A n-to-m decoder
n
a binary code of n bits = 2 distinct information
n
n input variables; up to 2 output lines
only one output can be active (high) at any time
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An implementation
Fig. 4.18
Three-to-eight-line decoder.
Digital Circuits
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Combinational logic implementation
each output = a minterm
use a decoder and an external OR gate to
implement any Boolean function of n input
variables
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Demultiplexers
a decoder with an enable input
receive informationin a single line and transmits
n
it in one of 2 possible output lines
Fig. 4.19
Two-to-four-line decoder with enable input
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3-to-8-Line
Decoder: example: Binary-to-octal conversion.
D0 = m0 = A2’A1’A0’
D1= m1 = A2’A1’A0
…etc
Expansion
two 3-to-8 decoder: a 4-to-16 deocder
Fig. 4.20
4 16 decoder
constructed with two
3 x 8 decoders
a 5-to-32 decoder?
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
Construct a 5-to-32-line decoder using four 3-8-line
decoders with enable inputs and a 2-to-4-line
decoder. A
0
3-8-line
Decoder
E
A1
A2
A3
A4
D0 – D7
3-8-line
Decoder
E
D8 – D15
3-8-line
Decoder
E
D16 – D23
3-8-line
Decoder
E
D24 – D31
2-4-line
Decoder
CS 151
Combination Logic Implementation
each output = a minterm
use a decoder and an external OR gate to
implement any Boolean function of n input
variables
A full-adder
S(x,y,z)=S(1,2,4,7)
C(x,y,z)=S(3,5,6,7)
Fig. 4.21
Implementation of a full adder with 1 decoder
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two possible approaches using decoder
OR(minterms of F): k inputs
NOR(minterms of F'): 2 - k inputs
n
In general, it is not a practical implementation
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4-10 Encoders
The inverse function of decoder
a decoder
z = D1 + D3 + D 5 + D 7
y = D2 + D3 + D 6 + D 7
x = D4 + D5 + D 6 + D 7
The encoder can be implemented
with three OR gates.
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An implementation
limitations
illegal input: e.g. D3=D6x1
The output = 111 (¹3 and ¹6)
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Priority Encoder
resolve the ambiguity of illegal inputs
only one of the input is encoded
D3 has the highest priority
D0 has the lowest priority
X: don't-care conditions
V: valid output indicator
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■ The maps for simplifying outputs x and y
fig. 4.22
Maps for a priority encoder
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■ Implementation of priority
Fig. 4.23
Four-input priority encoder
x = D2 + D3
x = D3 + D1D2
V = x 0 + D1 + D 2 + D 3
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4-11 Multiplexers
select binary information from one of many input
lines and direct it to a single output line
n
2 input lines, n selection lines and one output line
e.g.: 2-to-1-line multiplexer
Fig. 4.24
Two-to-one-line multiplexer
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4-to-1-line multiplexer
Fig. 4.25
Four-to-one-line multiplexer
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Note
n
n-to- 2 decoder
n
add the 2 input lines to each AND gate
OR(all AND gates)
an enable input (an option)
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Fig. 4.26
Quadruple two-to-one-line multiplexer
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Boolean function implementation
MUX: a decoders an OR gate
n
2 -to-1 MUX can implement any Boolean function
of n input variable
a better solution: implement any Boolean function
of n+1 input variable
n of these variables: the selection lines
the remaining variable: the inputs
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an example: F(A,B,C) = S(1,2,6,7)
Fig. 4.27
Implementing a Bolxean function with a multiplexer
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procedure:
assign an ordering sequence of the input variable
the rightmost variable (D) will be used for the input
lines
assign the remaining n-1 variables to the
Lines with construct the truth table
selection
lines w.r.t. their corresponding sequ
consider a pair of consecutive minterms starting
from m0
determine the input lines
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Example: F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15)
Fig. 4.28
Implementing a four-input function with a multiplexer
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Three-state gates
A multiplexer can be constructed with three-state
gates
Output state: 0, 1, and high-impedance (open ckts)
Fig. 4.29
Graphic symbol for a three-state buffer
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Example: Four-to-one-line multiplexer
Fig. 4.30
Multiplexer with three-state gates
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