Transcript SEQUENTIAL CIRCUITS

SEQUENTIAL CIRCUITS

DEFINITION OF SEQUENTIAL CIRCUIT



SYNCHRONOUS SEQUENTIAL CIRCUIT
ASYNCHRONOUS SEQUENTIAL CIRCUIT
MEMORY ELEMENTS
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
CLASSIFICATION: LATCHES AND FLIP-FLOPS
LATCHES
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BASIC LATCH
GATED LATCH
EFFECT OF PROPAGATION DELAYS
FLIP-FLOPS
ASYNCHRONOUS SEQUENTIAL CIRCUIT
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ASYNCHRONOUS BEHAVIOR
ANALYSIS OF ASYNCHROUNOUS CIRCUITS
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin. Revised 2005-02-14.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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DEFINITION OF SEQUENTIAL CIRCUIT

CIRCUITS IN WHICH THE VALUES OF THE OUTPUTS DEPENT
ON:
 THE PRESENT VALUES OF THE INPUTS
 THE PAST BEHAVIOR OF THE CIRCUIT
ARE CALLED SEQUENTIAL CIRCUIT.
IN SUCH CIRCUITS STORAGE ELEMENTS STORE
THE VALUES OF THE SIGNALS. THE CONTENTS OF THE
STORAGE ELEMENTS REPRESENT THE STATE OF THE
CIRCUIT.
THERE ARE TWO TYPES:


SYNCHRONOUS, AND
ASYNCHRONOUS
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DEFINITION OF SEQUENTIAL CIRCUIT
SYNCHRONOUS SEQUENTIAL CIRCUITS:
ARE SEQUENTIAL CIRCUITS CONTROLLED BY A CLOCK
SIGNAL
W
Combinational
circuit
Flip-flops
Q
Combinational
circuit
Z
Clock
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DEFINITION OF SEQUENTIAL CIRCUIT
ASYNCHRONOUS SEQUENTIAL CIRCUITS:
ARE SEQUENTIAL CIRCUITS:


WITH NO CLOCK SIGNALS,
NO FLIP-FLOPS TO STORE STATE VARIABLES
R
Y
y
Q
S

Feedback signal
Gate-delay
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MEMORY ELEMENTS
EXAMPLES OF MEMORY ELEMENTS:
A
B
Load
A
Data
B
Output
TG1
TG2
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MEMORY ELEMENTS
CLASSIFICATION: LATCHES AND FLIP-FLOPS
BASIC LATCH: is a feedback connection of two NOR gates or
two NAND gates.
GATED LATCH: is a basic latch that includes input gating and a
control input signal.
FLIP-FLOPS:
is a storage element based on the gated latch
principle which can have its output state
changed only at the edge of the controlling
clock signal.
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MEMORY ELEMENTS
CLASSIFICATION: LATCHES AND FLIP-FLOPS (Continues)


The state of the LATCH keeps changing according to the
values of the input signals during the period when the clock
is active.
The state of the FLIP-FLOP changes only at the edge of the
controlling clock signal.
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MEMORY ELEMENTS
LATCHES: BASIC LATCH
R
Qa
Qb
S
(a) Circuit
t1
R
S
Qa
Qb
t2
S
R
Qa Qb
0
0
1
1
0
1
0
1
0/1
0
1
0
1/0 (no change)
1
0
0
(b) Truth table
t3
t4
t5
t6
t7
t8
t9
t 10
1
0
1
0
1
?
0
1
?
0
Time
(c) Timing diagram
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MEMORY ELEMENTS
LATCHES: GATED RS LATCH
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MEMORY ELEMENTS

LATCHES: GATED D LATCH
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MEMORY ELEMENTS
EFFECT OF PROPAGATION DELAYS: Latch Setup and hold
times.
SETUP TIME: Minimum time that the D input signal must be stable prior to the
negative (positive) edge of the Clk (clock) signal.
HOLD TIME: Minimum time that the D input signal must remain stable after the
negative (positive) edge of the Clk (clock) signal
tsu
th
Clk
D
Q
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MEMORY ELEMENTS
FLIP-FLOPS:They are storage elements that can change their state no more than
once during one clock cycle. Two types: Master-Slave and Edge-triggered.

Master-Slave Flip-flop:
Master
D
Q
Q
D
D
Q
Slave
Qm
Clk Q
D
Q
Qs
Clk Q
Q
Q
(a) Circuit
(c) Graphical symbol
Clock
D
Qm
Q = Qs
(b) Timing diagram
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MEMORY ELEMENTS
FLIP-FLOPS (Continues).

Edge-triggered Flip-flop
1
P3
2
P1
3
P2
5
Q
6
Q
Clock
D
D
4
P4
(a) Circuit
Clock
Q
Q
(b) Graphical symbol
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MEMORY ELEMENTS

INPUT/OUTPUT BEHAVIOR OF LATCHES AND FLIP-FLOPS*
TYPES
WHEN INPUTS ARE SAMPLED
WHEN OUTPUTS ARE VALID
UNCLOCKED LATCH
(Basic latch)
ALWAYS
PROPAGATION DELAY FROM INPUT
CHANGE
LEVEL-SESITIVE LATCH
(Gated latch)
CLOCK HIGH
tsu , th around falling clock edge
PROPAGATION DELAY FROM INPUT
CHANGE
POSITIVE-EDGE FLIP-FLOP
CLOCK LOW-TO-HIGH TRANSITION
tsu , th around rising clock edge
PROPAGATION DELAY FROM RISING
EDGE OF CLOCK
NEGATIVE-EDGE FLIP-FLOP
CLOCK HIGH-TO-LOW TRANSITION
tsu , th around falling clock edge
PROPAGATION DELAY FROM FALLING
EDGE OF CLOCK
MASTER-SLAVE FLIP-FLOP
CLOCK HIGH-TO-LOW TRANSITION
tsu , th around falling clock edge
PROPAGATION DELAY FROM FALLING
EDGE OF CLOCK
_______________________________________
* Contemporary Logic Design by R.H. Katz, Benjamin Cummings, 1994, page 290.
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MEMORY ELEMENTS

LEVEL-SENSITIVE VERSUS EDGE-TRIGGERED STORAGE ELEMENTS
(a) Circuit
D
Clock
Clock
Q
Qa
Clk Q
Qa
Q
Qb
Q
Qb
Q
Qc
Q
Qc
D
D
D
Qa
Qb
Qc
D
(b) Timing diagram
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MEMORY ELEMENTS
FLIP-FLOPS (Continues)
CHARACTERISTIC AND EXCITATION EQUATIONS OF D, T AND J-K FLIP-FLOPS
Type
Symbol
Characteristic Excitation
D-type
Q
Clk
D
> !Q
T-type
T
Clk
>
Q
!Q
D Q+
0 0
1 1
Q Q+
0 0
0 1
1 0
1 1
D
0
1
0
1
T Q+
0 Q
1 !Q
Q Q+
0 0
0 1
1 0
1 1
T
0
1
1
0
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MEMORY ELEMENTS
FLIP-FLOPS (Continues)
CHARACTERISTIC AND EXCITATION EQUATIONS OF D, T AND J-K FLIP-FLOPS
Type
Symbol
J-K-type
J
K
Clk
SR-type
(not in use;
shown here for
completeness)
Clk
Q
!Q
>
S
R
>
Q
!Q
Characteristic
Excitation
J
0
0
1
1
K
0
1
0
1
Q+
Q
0
1
!Q
Q Q+
0 0
0 1
1 0
1 1
J
0
1
x
x
K
x
x
1
0
S
0
0
1
1
R
0
1
0
1
Q+
Q
0
1
Forbidden
Q Q+
0 0
0 1
1 0
1 1
S
0
1
0
x
R
x
0
1
0
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MEMORY ELEMENTS
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FLIP-FLOPS (Continues)
FLIP-FLOP CONVERSIONS : Given a flip-flop as a buiding block,
produce another type of flip-flop.
APPROACH: Determine the input logic to the given flip-flop by
satisfying the condition that both flip-flops must have identical
logic behavior (their outputs are the same)
A
X
IN P U T L O G IC
C IR C U IT
B
Y
G ive n
F L IP -F L O P
Q
Q
!Q
!Q
>

C lk
T H E S E P O IN T S
FO LLO W THE SAM E
L O G IC B E H A V IO R
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MEMORY ELEMENTS
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FLIP-FLOP CONVERSIONS (Continues):
Example: Produce the circuit of a J-K-type flip-flop using a T-type flipflop as a building block and NAND gates as needed
J K
Q
Q+JK
Q+T
T
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
JK
Q
0
1
00
0
0
01
0
1
11
1
1
10
1
0
T = J Q + K Q
T = J !Q + K Q
The corresponding circuit is shown on next slide
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MEMORY ELEMENTS
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
FLIP-FLOP CONVERSIONS:
Example (Continues): Circuit of a J-K flip-flop using a T flip-flop
J
K
C lk
T
SET
C LR
Q
Q
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ASYNCHRONOUS SEQUENTIAL CIRCUIT
IN SYNCHRONOUS SEQUENTIAL CIRCUITS A CLOCK SIGNAL CONSISTING
OF PULSES, CONTROLS THE STATE VARIABLES WHICH ARE
REPRESENTED BY FLIP-FLOPS. THEY ARE SAID TO OPERATE IN
PULSE MODE.
IN ASYNCHRONOUS CIRCUITS STATE CHANGES ARE NOT TRIGGERED BY
CLOCK PULSES. THEY DEPEND ON THE VALUES OF THE INPUT AND
FEEDBACK VARIABLES.
TWO CONDITIONS FOR PROPER OPERATION:
1.-INPUTS TO THE CIRCUIT MUST CHANGE ONE AT A TIME AND MUST
REMAIN CONSTANT UNTIL THE CIRCUIT REACHES STABLE STATE.
2.-FEEDBACK VARIABLES SHOULD CHANGE ALSO ONE AT A TIME. WHEN
ALL INTERNAL SIGNALS STOP CHANGING, THEN THE CIRCUIT IS
SAID TO HAVE REACHED STABLE STATE.
WHEN THE INPUTS SATISFY CONDITION 1 ABOVE, THEN THE CIRCUIT IS
SAID TO OPERATE IN FUNDAMENTAL MODE.
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ASYNCHRONOUS SEQUENTIAL CIRCUIT
ASYNCHRONOUS BEHAVIOR
Consider the Set-Reset latch.
 The gates shown below have no delay. Their delay (twice
one-gate delay) is represented by the square.
R
Y
y
Q
S
(a) Circuit with modeled gate delay
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ASYNCHRONOUS SEQUENTIAL CIRCUIT
ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues)

The circuit behavior is represented by a State-assigned table or Flow table
which show every possible transition of the circuit for each input value.
Stable-states are those circled in the table because, while the inputs are
stable, present state is equal to next state (internal variables stop
changing). Columns with no circled sates indicate circuit oscillation for that
particular input value.
Present
state
y
0
1
Next state
SR = 00
01
10
11
Y
Y
Y
Y
0
1
0
0
1
1
0
0
(b) State-assigned table
Figure 9.1. Analysis of the S-R latch.
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ASYNCHRONOUS SEQUENTIAL CIRCUIT

ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues)
FINITE-STATE-MACHINE MODEL: MOORE MODEL
Present
state
A
B
Next state
SR = 00 01 10
A A
B
B A
B
11
A
A
Output
Q
0
1
(a) State table
SR
10
00
01
11
A 0
B 1
00
10
01
11
(b) State diagram
Figure 9.2. FSM model for the SR latch. MOORE MODEL
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ASYNCHRONOUS SEQUENTIAL CIRCUIT

ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues)
FINITE-STATE-MACHINE MODEL: MEALY MODEL
Next state
Present
state
SR = 00 01 10
Output, Q
11
00
01
10
11
A
A
A
B
A
0
0
–
0
B
B
A
B
A
1
–
1
–
SR/Q
10/ –
(a) State Table
00/0
01/0
11/0
(b) State Diagram
A
B
00/1
10/1
01  –
11  –
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ASYNCHRONOUS SEQUENTIAL CIRCUIT
ANALYSIS OF ASYNCHROUNOUS CIRCUITS
PROCEDURE:
 CUT ALL FEEDBACK PATHS AND INSERT A DELAY ELEMENT
AT EACH POINT WHERE CUT WAS MADE
 INPUT TO THE DELAY ELEMENT IS THE NEXT STATE
VARIABLE Yi WHILE THE OUTPUT IS THE PRESENT VALUE
yi.
 DERIVE THE NEXT-SATE AND OUTPUT EXPRESSIONS FROM
THE CIRCUIT
 DERIVE THE EXCITATION TABLE
 DERIVE THE FLOW TABLE
 DERIVE A STATE-DIAGRAM FROM THE FLOW TABLE
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ASYNCHRONOUS SEQUENTIAL CIRCUIT

ANALYSIS OF ASYNCHROUNOUS CIRCUITS: EXAMPLE
D
Y
y
Q
C
(a) Circuit
Present
state
y
Next state
CD = 00
Present
state
01
10
11
Y
Y
Y
Y
Q
0
0
0
0
1
0
1
1
1
0
1
1
Next state
CD = 00
01
10
11
Q
A
A
A
A
B
0
B
B
B
A
B
1
(c) Flow table
(b) Excitation table
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ASYNCHRONOUS SEQUENTIAL CIRCUIT

ANALYSIS OF ASYNCHROUNOUS CIRCUITS: EXAMPLE CONTINUES
Present
state
Next state
CD = 00
01
10
11
Q
A
A
A
A
B
0
B
B
B
A
B
1
(c) Flow Table
11
CD
0x
x0
A 0
B 1
0x
x1
10
(d) State Diagram: Moore Model
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ASYNCHRONOUS SEQUENTIAL CIRCUIT

SYNTHESIS OF ASYNCHROUNOUS CIRCUITS

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
THIS TOPIC IS NOT COVERED IN THIS COURSE. IT BELONGS TO A
MORE ADVANCED LOGIC DESIGN COURSE.
THIS SUBJECT IS VERY IMPORTANT IN TODAYS DIGITAL SYSTEMS
DESIGN BECAUSE CLOCKS ARE SO FAST THAT THEY PRESENT
PROPAGATION DELAYS MAKING SUBSYSTEMS TO OPERATE OUT
OF SYNCHRONIZATION.
TECHNIQUES FOR SYNTHESIS OF ASYNCHRONOUS CIRCUITS
INCLUDE
 THE HOFFMAN OR CLASSIC SYNTHESIS APPROACH
 HANDSHAKING SIGNALING FOR TWO SUBSYSTEMS TO
COMMUNICATE ASYNCHRONOUSLY
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